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| |'''Pin Name''' | | |'''Pin Name''' |
| |'''Description''' | | |'''Description''' |
− | |'''Connect To''' | + | |'''During Programming<br>Connect To''' |
| + | |'''After Programming<br>Connect To''' |
| |'''Notes''' | | |'''Notes''' |
| |--- | | |--- |
| |M0 | | |M0 |
| |Mode select pin for configuration | | |Mode select pin for configuration |
− | |Ground (during programming) | + | |Ground |
| + | |User I/O |
| | rowspan=3 | Should be low during configuration to give <0:0:0> | | | rowspan=3 | Should be low during configuration to give <0:0:0> |
| See [[FPGA programming modes]] | | See [[FPGA programming modes]] |
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| |M1 | | |M1 |
| |Mode select pin for configuration | | |Mode select pin for configuration |
− | |Ground (during programming) | + | |Ground |
| + | |User I/O |
| |---- | | |---- |
| |M2 | | |M2 |
| |Mode select pin for configuration | | |Mode select pin for configuration |
− | |Ground (during programming) | + | |Ground |
| + | |User I/O |
| |---- | | |---- |
| |DONE | | |DONE |
| |Programming complete pin | | |Programming complete pin |
| + | |FPGA programmer |
| |FPGA programmer | | |FPGA programmer |
| |Goes high when programming is complete | | |Goes high when programming is complete |
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| |PROG_B | | |PROG_B |
| |Initiates programming process | | |Initiates programming process |
| + | |FPGA programmer |
| |FPGA programmer | | |FPGA programmer |
| |Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation | | |Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation |
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| |CCLK | | |CCLK |
| |Clock for programming | | |Clock for programming |
− | |FPGA programmer? | + | |EEPROM clock input pin |
| + | |User I/O |
| |If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input | | |If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input |
| |---- | | |---- |
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| |Programming status indicator | | |Programming status indicator |
| |FPGA programmer | | |FPGA programmer |
− | |Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error | + | |User I/O, or ground |
| + | |Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error<br>After programming, should be driven high or <br>low if not used for user I/O |
| |---- | | |---- |
| |PUDC_B | | |PUDC_B |
| |User I/O pull-up control | | |User I/O pull-up control |
| |FPGA programmer | | |FPGA programmer |
| + | |User I/O |
| |Set low during programming to enable pull-ups on all user I/O pins<br>after configuration | | |Set low during programming to enable pull-ups on all user I/O pins<br>after configuration |
| |---- | | |---- |
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| |Serial data input | | |Serial data input |
| |EEPROM serial data output | | |EEPROM serial data output |
| + | |User I/O |
| |Serial data input from EEPROM - used only in serial [[FPGA programming modes | FPGA programming mode]] | | |Serial data input from EEPROM - used only in serial [[FPGA programming modes | FPGA programming mode]] |
| |---- | | |---- |
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| |Serial data output | | |Serial data output |
| |''No connection'' | | |''No connection'' |
| + | |User I/O |
| |Used to daisy chain to next FPGA, if this were a multi-FPGA design<br>We are using only one FPGA per PCB, so this is not used | | |Used to daisy chain to next FPGA, if this were a multi-FPGA design<br>We are using only one FPGA per PCB, so this is not used |
| |---- | | |---- |
| |VS0 | | |VS0 |
| |Variant select pin for SPI mode programming | | |Variant select pin for SPI mode programming |
− | |FPGA programmer | + | |Ground |
− | | rowspan=3 | See [[FPGA programming modes#SPI mode]] | + | |User I/O |
| + | | rowspan=3 | Tied low during programming since we are not using SPI mode programming<br>''Perhaps can be left unconnected during programming???'' |
| |---- | | |---- |
| |VS1 | | |VS1 |
| |Variant select pin for SPI mode programming | | |Variant select pin for SPI mode programming |
− | |FPGA programmer | + | |Ground |
| + | |User I/O |
| |---- | | |---- |
| |VS2 | | |VS2 |
| |Variant select pin for SPI mode programming | | |Variant select pin for SPI mode programming |
− | |FPGA programmer | + | |Ground |
| + | |User I/O |
| |---- | | |---- |
| |} | | |} |