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| This section defines some pins that must be on the FPGA, and what they must connect to. Many of these connections may also be found in the [[#IC netlist|IC netlist]]. | | This section defines some pins that must be on the FPGA, and what they must connect to. Many of these connections may also be found in the [[#IC netlist|IC netlist]]. |
| | | |
− | "Pin Name" defines the name of the pins as they will be used for our project, not the actual pin name in the FPGA schematic. | + | === Custom I/O pins === |
| + | |
| + | For these I/O pins, "Pin Name" defines the name of the pins as they will be used for our project, not the actual pin name in the FPGA schematic. |
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| {| cellpadding=3 border=1 | | | {| cellpadding=3 border=1 | |
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| |Backplane | | |Backplane |
| |---- | | |---- |
| + | |} |
| + | |
| + | === Configuration Pins === |
| + | |
| + | These pins are used for the programming of the FPGA. |
| + | {| cellspacing=3 border=1 | |
| + | |'''Pin Name''' |
| + | |'''Description''' |
| + | |'''Connect To''' |
| + | |'''Notes''' |
| + | |--- |
| |M0 | | |M0 |
| |Mode select pin for configuration | | |Mode select pin for configuration |
| |FPGA programmer | | |FPGA programmer |
| + | | |
| |---- | | |---- |
| |M1 | | |M1 |
| |Mode select pin for configuration | | |Mode select pin for configuration |
| |FPGA programmer | | |FPGA programmer |
| + | | |
| |---- | | |---- |
| |M2 | | |M2 |
| |Mode select pin for configuration | | |Mode select pin for configuration |
| |FPGA programmer | | |FPGA programmer |
| + | | |
| |---- | | |---- |
| + | |DONE |
| + | |Programming complete pin |
| + | |FPGA programmer? |
| + | |Goes high when programming is complete |
| + | |---- |
| + | |PROG_B |
| + | |Initiates programming process |
| + | |FPGA programmer |
| + | |Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation |
| + | |---- |
| + | |CCLK |
| + | |Clock for programming |
| + | |FPGA programmer? |
| + | |If M0-M2 define a master mode, CCLK is internally generated<br>If M0-M2 define a slave mode, CCLK is a clock input |
| + | |---- |
| + | |INIT_B |
| + | |Programming status indicator |
| + | |FPGA programmer |
| + | |Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error |
| + | |---- |
| |} | | |} |
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