Difference between revisions of "Programming the SPI"
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| − | + | The ADC ([http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html AD7928]) and Temperature Sensor ([http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html AD7314]) communicate over very similar, SPI-like interfaces. It was therefore decided that the controllers for these chips should be merged into a single module in the FPGA. The combined module serves to abstract the details of the communication protocol with these sensors. | |
| − | + | ||
| − | * | + | == SPI Module Interface == |
| − | The | + | |
| − | + | * inputs | |
| − | + | ** Clk: Clock | |
| + | ** /Rst: asynchronous, active-low reset | ||
| + | ** Go: pulse to begin sensor data request process | ||
| + | ** T_/A: Chip select: high-Temp, low-ADC | ||
| + | ** Addr: 3-bit address of the desired ADC line (ignored if not applicable)<br> | ||
| + | ** SDO: serial data from the sensors | ||
| + | |||
| + | * outputs | ||
| + | ** SCLK: Clock output | ||
| + | ** /Rsi_out: asynchronous, active low reset output | ||
| + | ** SDI: serial control word line | ||
| + | ** A_/CS: active low chip select line for the ADC | ||
| + | ** T_CE: active high chip select line for the Temperature Sensor | ||
| + | ** Done: pulse to signal data availability on appropriate bus | ||
| + | ** A_Q: 12-bit ADC data output bus | ||
| + | ** A_A: 3-bit address of the ADC line returning data | ||
| + | ** T_Q: 10-bit Temperature sensor data output bus | ||
| + | |||
| + | |||
| + | == SPI Module Components == | ||
| + | |||
| + | The components of this module follow directly from its predecessors (see [[Programming the temperature sensor]] and [[Programming the ADC]]). Two important components were added, however, to further abstract ADC communication protocol via "Process Control" (A_proccontrol) unit and to properly supervise the chip's reset cycle (ADCreset). | ||
| + | |||
| + | The ADC requires two dummy conversations upon reset or startup. The ADCreset unit forces these two cycles to take place. A request for data on a new ADC line (compared to last request) requires one write cycle to the ADC control buffer and then the ordinary read cycle. A_proccontrol determines whether to perform a write cycle. The "Done" pulse is withheld if the competed cycle is a control buffer write cycle or reset cycles mentioned above. Only the final read cycle merits the external "Done" pulse. | ||
Latest revision as of 14:48, 24 June 2008
The ADC (AD7928) and Temperature Sensor (AD7314) communicate over very similar, SPI-like interfaces. It was therefore decided that the controllers for these chips should be merged into a single module in the FPGA. The combined module serves to abstract the details of the communication protocol with these sensors.
SPI Module Interface
- inputs
- Clk: Clock
- /Rst: asynchronous, active-low reset
- Go: pulse to begin sensor data request process
- T_/A: Chip select: high-Temp, low-ADC
- Addr: 3-bit address of the desired ADC line (ignored if not applicable)
- SDO: serial data from the sensors
- outputs
- SCLK: Clock output
- /Rsi_out: asynchronous, active low reset output
- SDI: serial control word line
- A_/CS: active low chip select line for the ADC
- T_CE: active high chip select line for the Temperature Sensor
- Done: pulse to signal data availability on appropriate bus
- A_Q: 12-bit ADC data output bus
- A_A: 3-bit address of the ADC line returning data
- T_Q: 10-bit Temperature sensor data output bus
SPI Module Components
The components of this module follow directly from its predecessors (see Programming the temperature sensor and Programming the ADC). Two important components were added, however, to further abstract ADC communication protocol via "Process Control" (A_proccontrol) unit and to properly supervise the chip's reset cycle (ADCreset).
The ADC requires two dummy conversations upon reset or startup. The ADCreset unit forces these two cycles to take place. A request for data on a new ADC line (compared to last request) requires one write cycle to the ADC control buffer and then the ordinary read cycle. A_proccontrol determines whether to perform a write cycle. The "Done" pulse is withheld if the competed cycle is a control buffer write cycle or reset cycles mentioned above. Only the final read cycle merits the external "Done" pulse.