| Line 3: | Line 3: | 
|  | The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values. |  | The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values. | 
|  |  |  |  | 
|  | + | The mask selects which channels must be altered. Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 0  and the LSB of the fourth byte will be channel 31.  Thus, if only channels 14 through 26 are to be programmed, the mask would contain: | 
|  | + | {| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left" | 
|  | + | ! First data byte | 
|  | + | | 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 | 
|  | + | |- | 
|  | + | ! Second data byte | 
|  | + | | 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 | 
|  | + | |- | 
|  | + | ! Third data byte | 
|  | + | | 1 || 1 || 0 || 0 || 0 || 0 || 0 || 0 | 
|  | + | |- | 
|  | + | ! Fourth data byte | 
|  | + | | 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 | 
|  | + | |} | 
|  |  |  |  | 
|  | == Programming Details == |  | == Programming Details == | 
|  |  |  |  | 
| − | [[Image:P-packetPayload.png|thumb|P-packet Format]] | + | [[Image:P-packetPayload.png|frame|P-packet Format]] | 
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|  |  |  |  | 
| Line 18: | Line 32: | 
|  |  |  |  | 
|  |  |  |  | 
| − | Write signals to the [[Programming_the_DAC|DAC Controller]] | + | Write signals to the [[Programming_the_DAC|DAC Controller]] and [[FPGA_Registers#DAC Register|DAC Register]] | 
|  | * ''DAC_iGo'': [out] active-low "Go" signal |  | * ''DAC_iGo'': [out] active-low "Go" signal | 
|  | + | * ''DACReg_En'': Enable (write) signal to DAC Register | 
|  | * ''DAC_Addr'': [out] 5-bit DAC channel address   |  | * ''DAC_Addr'': [out] 5-bit DAC channel address   | 
| − | [the 14-bitDAC valueis synonymous with that passed to the DACregister. See below.] | + | * ''DAC_D'': [out] 14-bit voltage value for the register and DAC Controller | 
|  | + | * ''DAC_Done'': [in] "Done programming" signal from DAC controller | 
|  |  |  |  | 
|  |  |  |  | 
| Line 28: | Line 44: | 
|  | * ''state_D'': [out] (3-bit) state register input |  | * ''state_D'': [out] (3-bit) state register input | 
|  | * ''state_Q'': [in] (3-bit) state register output |  | * ''state_Q'': [in] (3-bit) state register output | 
| − | 
 |  | 
| − | 
 |  | 
| − | [[FPGA_Registers#DAC Register|DAC Register]] control lines
 |  | 
| − | * ''DACReg_En'': [out] ;
 |  | 
| − | * ''--DACReg_Addr'': [out] _VECTOR (4 downto 0);
 |  | 
| − | * ''DACReg_D'': [out] 14-bit voltage value for the register and DAC Controller
 |  | 
| − | * ''DACReg_Q'': [in] _VECTOR (15 downto 0);
 |  | 
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|  |  |  |  |