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− | == (010) Idle ==
| + | :''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.'' |
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− | Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.
| + | = (010) Idler = |
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− | inputs
| + | The Idler Block corresponding to state 010 continuously is the default module running an "idle process". It awaits an interrupt corresponding to "Receive FIFO non-empty", unpon which it transitions to state 011 - [[FPGA_Reader|Read]]. |
− | * ''Clk'': clock
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− | * ''/Rst'': asynchronous, active-low reset
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− | * ''state_in'': 3-bit state value
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− | * ''TxRx_D'': 8-bit data from transceiver
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− | * ''TxRx_Done'': pulse from transceiver to signal transfer complete
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− | * ''TxRx_Go'': transceiver go line
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− | * ''TxRx_R/W'': read/write flag for transceiver
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− | * ''TxRx_Aout'': register address bus for transceiver
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| + | == Programming Details == |
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− | blocks
| + | The Idler is essentially a state-conscious wrapper around an ''INTCatcher'' module instatiation to which the interrupt mask "1000" is passed (selecting the "Rx FIFO non-empty" interrupt as opposed to "Self-Initialization Complete" etc.) INTCatcher only returns a "Done" pulse when the requested interrupt was found so the change of state to "Read" (011) is set to trigger on this "Done" signal. |
− | * '''Request INT0RD''' (0x76) register via <tt>reqFromAddr</tt> pulsed by the ''LoopEn'' signal from Looper (below).
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− | * '''Looper'''
| + | === Ports === |
− | ** Switch to determine if this state should loop on itself or continue to the next state.
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− | ** inputs
| + | * ''Clk'': [in] clock |
− | *** ''S_En'': state enable
| + | * ''Rst: [in] asynchronous reset |
− | *** ''TxRx_Done'': ''Done'' pulse from transceiver | + | |
− | *** ''TxRx_Data'': ''D_out'' bus from transceiver
| + | * ''Eth_iINT'': [in] EC interrupt pin |
− | ** outputs
| + | * ''state_in'': [in] 3-bit FPGA state value |
− | *** ''LoopEn'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
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− | *** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
| + | [[FPGA_Transceiver|Transceiver]] Control Lines |
− | *** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high
| + | * ''TxRx_Din'': [in] EC control register return value |
| + | * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]. |
| + | * ''TxRx_Go'': [out] "Go" signal to read an EC control register byte |
| + | * ''TxRX_RiW'': [out] active-high read, active-low write flag |
| + | * ''TxRx_Aout'': [out] EC control register address (8-bit) |