FPGA Reset

(00X) Reset Modules

The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)

The control packets leading to states 00X pertaining to thes reset modules are:

Packet Type Byte	Hex value	Bin value	Description
R	0x52	0101 0010
"R'"	0xD2	1101 0010

• Clk: [in] clock

Reset Signals

• Rst: [in] asynchronous reset
• Eth_iRst: [inout] EC active-low reset pin
• Eth_iINT: [in] EC active-low interrupt signal

State Register Control Lines

• state_En: [out] state register enable (write) signal
• state_D: [out] (3-bit) state register input
• state_Q: [in] (3-bit) state register output

MAC Address Register Control Lines

• MACregs_En: [out] register enable (write) signal
• MACregs_A: [out] byte address (4-bit)
• MACregs_D: [out] 8-bit input value

Transceiver Control Lines

• TxRx_Go: [out] "Go" signal to read/write an EC control register byte
• TxRx_Aout: [out] EC control register address (8-bit)
• TxRx_Dout: [out] EC control register write value
• TxRx_RiW: [out] active-high read, active-low write flag
• TxRx_Din: [in] EC control register return value
• TxRx_Done: [in] "Done" signal from Transceiver.

• dbShort: [in] debug signal to bypass EC reset waiting periods