Difference between revisions of "FPGA Reset"
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== (000) Reset Cycle == | == (000) Reset Cycle == | ||
− | Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet | + | Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet Controller (EC), and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]]. |
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− | + | * ''Clk'': [in] clock | |
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− | + | Reset Signals | |
− | + | * ''Rst: [in] asynchronous reset | |
− | + | * ''Eth_iRst'': [inout] EC active-low reset pin | |
− | + | * ''Eth_iINT'': [in] EC active-low interrupt signal | |
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− | + | [[FPGA_Register#State_Register|State Register]] Control Lines | |
− | + | * ''state_En'': [out] state register enable (write) signal | |
− | + | * ''state_D'': [out] (3-bit) state register input | |
− | + | * ''state_Q'': [in] (3-bit) state register output | |
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− | + | MAC Address Register Control Lines | |
− | + | * ''MACregs_En'': [out] register enable (write) signal | |
− | + | * ''MACregs_A'': [out] byte address (4-bit) | |
− | + | * ''MACregs_D'': [out] 8-bit input value | |
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− | + | [[FPGA_Transceiver|Transceiver]] Control Lines | |
− | + | * ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte | |
− | + | * ''TxRx_Aout'': [out] EC control register address (8-bit) | |
− | + | * ''TxRx_Dout'': [out] EC control register write value | |
− | + | * ''TxRx_RiW'': [out] active-high read, active-low write flag | |
− | + | * ''TxRx_Din'': [in] EC control register return value | |
− | + | * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]. | |
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− | + | * ''dbShort'': [in] debug signal to bypass EC reset waiting periods | |
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Revision as of 18:25, 29 May 2008
(000) Reset Cycle
Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet Controller (EC), and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see Reset and Initialization.
- Clk: [in] clock
Reset Signals
- Rst: [in] asynchronous reset
- Eth_iRst: [inout] EC active-low reset pin
- Eth_iINT: [in] EC active-low interrupt signal
State Register Control Lines
- state_En: [out] state register enable (write) signal
- state_D: [out] (3-bit) state register input
- state_Q: [in] (3-bit) state register output
MAC Address Register Control Lines
- MACregs_En: [out] register enable (write) signal
- MACregs_A: [out] byte address (4-bit)
- MACregs_D: [out] 8-bit input value
Transceiver Control Lines
- TxRx_Go: [out] "Go" signal to read/write an EC control register byte
- TxRx_Aout: [out] EC control register address (8-bit)
- TxRx_Dout: [out] EC control register write value
- TxRx_RiW: [out] active-high read, active-low write flag
- TxRx_Din: [in] EC control register return value
- TxRx_Done: [in] "Done" signal from Transceiver.
- dbShort: [in] debug signal to bypass EC reset waiting periods