Difference between revisions of "Programming the SPI"
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=== ADC/Temperature Sensor Integration === | === ADC/Temperature Sensor Integration === | ||
− | The ADC ([http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html AD7928]) and Temperature Sensor ([http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html AD7314]) communicate over very similar, SPI-like interfaces. | + | The ADC ([http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html AD7928]) and Temperature Sensor ([http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html AD7314]) communicate over very similar, SPI-like interfaces. It was therefore decided that the controllers for these chips should be merges into a single module in the FPGA. The combined module serves to abstract the details of the communication protocol with these sensors. |
+ | |||
+ | * inputs | ||
+ | ** Clk: Clock | ||
+ | ** /Rst: asynchronous, active-low reset | ||
+ | |||
+ | ** Go: pulse to begin sensor data request process | ||
+ | ** T_/A: Chip select: high-Temp, low-ADC | ||
+ | ** Addr: 3-bit address of the desired ADC line (ignored if not applicable)<br> | ||
+ | ** SDO: serial data from the sensors | ||
+ | |||
+ | * outputs | ||
+ | ** SCLK: Clock output | ||
+ | ** /Rsi_out: asynchronous, active low reset output | ||
+ | ** SDI: serial control word line | ||
+ | ** A_/CS: active low chip select line for the ADC | ||
+ | ** T_CE: active high chip select line for the Temperature Sensor | ||
+ | ** Done: pulse to signal data availability on appropriate bus | ||
+ | ** A_Q: 12-bit ADC data output bus | ||
+ | ** A_A: 3-bit address of the ADC line returning data | ||
+ | ** T_Q: 10-bit Temperature sensor data output bus | ||
+ | |||
----------------- | ----------------- |
Revision as of 06:03, 28 October 2007
This page discusses a project currently under development. Please be aware that information on this page may change as the project progresses.
ADC/Temperature Sensor Integration
The ADC (AD7928) and Temperature Sensor (AD7314) communicate over very similar, SPI-like interfaces. It was therefore decided that the controllers for these chips should be merges into a single module in the FPGA. The combined module serves to abstract the details of the communication protocol with these sensors.
- inputs
- Clk: Clock
- /Rst: asynchronous, active-low reset
- Go: pulse to begin sensor data request process
- T_/A: Chip select: high-Temp, low-ADC
- Addr: 3-bit address of the desired ADC line (ignored if not applicable)
- SDO: serial data from the sensors
- outputs
- SCLK: Clock output
- /Rsi_out: asynchronous, active low reset output
- SDI: serial control word line
- A_/CS: active low chip select line for the ADC
- T_CE: active high chip select line for the Temperature Sensor
- Done: pulse to signal data availability on appropriate bus
- A_Q: 12-bit ADC data output bus
- A_A: 3-bit address of the ADC line returning data
- T_Q: 10-bit Temperature sensor data output bus
This module aims to merge the ADC and temperature sensor modules into a single module. Both modules communicate over a shared SPI-like bus, and there are many structural and functional similarities between the two. However, this is a partially completed project. The current VHDL files (which are mostly written but need to be tested) can be found at:
The subprojects (i.e. earlier versions of the separate ADC and temperature sensor modules) can be found at: