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Programming the Ethernet controller (view source)
Revision as of 19:36, 19 July 2007
, 19:36, 19 July 2007no edit summary
** outputs
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus
=== (000) Reset Cycle ===
=== (000) Reset Cycle ===
This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.
This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; tied to 111
=== (111) Transmit "D" ===
=== (111) Transmit "D" ===
This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.
This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.