Line 31: |
Line 31: |
| ** inouts | | ** inouts |
| *** ''AD'': 8-bit address and data bus | | *** ''AD'': 8-bit address and data bus |
| + | |
| + | === (000) Reset Cycle === |
| + | |
| + | inputs |
| + | * State: 3-bit state value |
| + | * D_En: DAC enable, assume held high/low by previous block |
| + | * A_En: ADC enable, assume held high/low by previous block |
| + | * E_En: Ethernet enable, assume held high/low by previous block |
| + | |
| + | internal signals |
| + | * S_En: state enable, S_En <= not (St(2) or St(1) or St(0)) |
| + | * Go: when S_En goes high Go pulses for one cycle |
| + | * D_Go: DAC reset go pulse, D_Go <= Go and D_En |
| + | * A_Go: ADC reset go pulse, A_Go <= Go and A_En |
| + | * E_Go: Ethernet reset go pulse, E_Go <= Go and E_En |
| + | |
| + | blocks |
| + | * DAC Reset: |
| + | ** Resets and initializes the DAC. |
| + | ** inputs |
| + | *** Clk: clock |
| + | *** /Rst: asynchronous, active-low reset |
| + | *** D_Go: go pulse to begin reset/initialization process |
| + | ** outputs |
| + | *** - All DAC reset/initialization control lines - |
| + | *** D_Done: goes high when reset/initialization process is complete, falls on D_Go pulse |
| + | * ADC Reset: |
| + | ** Resets and initializes the ADC. |
| + | ** inputs |
| + | *** Clk: clock |
| + | *** /Rst: asynchronous, active-low reset |
| + | *** A_Go: go pulse to begin reset/initialization process |
| + | ** outputs |
| + | *** - All ADC reset/initialization control lines - |
| + | *** A_Done: goes high when reset/initialization process is complete, falls on A_Go pulse |
| + | * Ethernet Reset: |
| + | ** Resets and initializes the Ethernet controller. |
| + | ** inputs |
| + | *** Clk: clock |
| + | *** /Rst: asynchronous, active-low reset |
| + | *** E_Go: go pulse to begin reset/initialization process |
| + | ** outputs |
| + | *** - All Ethernet reset/initialization control lines - |
| + | *** E_Done: goes high when reset/initialization process is complete, falls on E_Go pulse |
| + | * Coordinator |
| + | ** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete. Has internal signal: |
| + | :Flag <= (D_Done or not D_En) and (A_Done or not A_En) and (E_Done or not E_En) |
| + | ** inputs |
| + | *** Clk: clock |
| + | *** /Rst: asynchronous, active-low reset |
| + | *** D_En: high when DAC is to be reset |
| + | *** D_Done: high when DAC is done resetting |
| + | *** A_En: high when ADC is to be reset |
| + | *** A_Done: high when ADC is done resetting |
| + | *** E_En: high when Ethernet controller is to be reset |
| + | *** E_Done: high when Ethernet controller is done resetting |
| + | ** outputs |
| + | *** Done: when Flag goes high, Done pulses for one cycle; connects to state counter as an enable (thereby incrementing the state to 001) |