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Programming the Ethernet controller (view source)
Revision as of 19:39, 18 July 2007
, 19:39, 18 July 2007no edit summary
== Controller ==
== Controller ==
* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus