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Now that we've discussed VHDL itself, it's time to learn the development environment. If you don't already have it installed, you will want to install the [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK]. The ISE Foundation is a professional tool that will cost you an arm and a leg. The ISE WebPACK is a free version of the software that does most of what you need (unless you have large, complex designs or are working with the newest and best Xilinx FPGAs). If you know ahead of time which series of FPGAs you plan to use, you can save time and disk space by only installing the files for that FPGA series. Once you've got that installed, fire it up.
Now that we've discussed VHDL itself, it's time to learn the development environment. If you don't already have it installed, you will want to install the [http://www.xilinx.com/ise/logic_design_prod/webpack.htm Xilinx ISE WebPACK]. The ISE Foundation is a professional tool that will cost you an arm and a leg. The ISE WebPACK is a free version of the software that does most of what you need (unless you have large, complex designs or are working with the newest and best Xilinx FPGAs). If you know ahead of time which series of FPGAs you plan to use, you can save time and disk space by only installing the files for that FPGA series. Once you've got that installed, fire it up.
If you find this tutorial a bit lacking, then you'll want to look over the [http://toolbox.xilinx.com/docsan/xilinx9/books/manuals.pdf ISE manuals].
== Creating a new project ==
== Creating a new project ==
[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]
[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]
Once you've synthesized your design, double click on "View RTL Schematic". RTL stands for Register Transfer Level. This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together. As discussed in previous sections, a thick wire is a bus. By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus. Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows. Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows. Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other.
Once you've synthesized your design, double click on "View RTL Schematic". RTL stands for Register Transfer Level. This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together. As discussed in previous sections, a thick wire is a bus. By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus. Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows. Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows. Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other. To enter a block, simply double click on it. To exit a block and go back to the next higher schematic, you can right click and select "Pop to the Calling Schematic."
You can also double click "View Technology Schematic." This is similar to the RTL schematic, however there is no blocking of components together functionally, nor will multiple lines be combined into buses. It can be a rather large, intimidating, and confusing view so it is not often used, as RTL gives the same information in a much more comprehensible fashion.
== Simulation ==
== Simulation ==
Now that you've written your code and seen the RTL schematic (then fixed your code and seen the new RTL schematic and repeated that whole process a few times) it's time to see if it actually works. To do that you need to run a simulation. Unfortunately, it's not that easy; you first need to define a '''test bench waveform''' (.tbw) file.
[[Image:ISE - Make New TBW.PNG|thumb|right|125px|Dialog box for creating a new test bench waveform.]]
Go to '''Project > New Source''' and select "Test Bench Waveform." Give the file a name and choose a parent directory, then click next. The next dialog box will ask you which source file to associate with the text bench waveform file. Select the file you wish to text and click next. Verify the details you just selected and click finish. This will bring up the dialog box shown to the right. Chances are you won't need to change (or even worry about) most of that window. However in the bottom right corner you can see "Initial Length of Test Bench". The default value for that tends to be too small for a design of any size; I generally set it to 10,000. You can try to be clever and change it from 10,000 ns to 10<math>\mu</math>s, but it won't work; changing the time unit adjusts other values across the dialog box. So just type in "10000" (or whatever other number you feel is best).
If you have an existing .tbw file that you want to use, go to the Sources box, change the pull-down menu to "Behavioral Simulation", and double click on the file you want.
[[Image:ISE - TBW.PNG|thumb|left|125px|Test bench waveform editor.]]
So now you have your test bench waveform open. Your screen will look something along the lines of the one shown to the left. In the main section of the screen you see the waveforms for the inputs and outputs. You can change which waveforms are shown. To delete a waveform, click on the name and press the delete key. To add a waveform (including internal signals if you want to monitor those), go to the Processes box in the bottom left and double click on the name of the signal you wish to add to the waveform.
A line will appear as a waveform like the ones in the image. A bus will appear as a thick line with a value on the line and a narrow point at a transition. You can set whether the value is to be displayed in hex, binary, or decimal. You can also click the plus sign next to the name to expand the bus into a set of lines.
To set the values, simply click on the waveforms wherever you want the value to be toggled. If you wish to use one of the 7 non-binary logic levels ([[VHDL_tutorial#VHDL_Resolution_Table|shown here]]) or to set a pattern for ISE to fill in for you, right click on the waveform where you wish to start the pattern or non-binary logic level and select "Set Value." Beware of having too many transitions, as it is possible to crash the program that way.
[[Image:ISE - Simulation.PNG|thumb|right|125px|Simulation results view.]]
Once you have defined your input waveforms (don't bother trying to set your output waveforms; those get defined by the simulator), you are now ready to simulate. Go to the Processes box and double click "Simulate Behavioral Model" (under "Xilinx ISE Simulator"). ISE will think for a bit then open a new window like the one shown to the right. This shows the input and output signal waveforms. You can see the internal bus ''count'' (highlighted) expanded to show both the bus notation mentioned above (values in hex) and the individual line waveforms. You'll have to study these waveforms closely to debug many of your designs. Timing hazards may appear here (a signal fires a clock cycle too early or too late and ruins the synchronization of the entire device, etc.). If you look over this design and decide you are happy with the output, then you have successfully designed and done basic testing in VHDL.
== Going further with ISE ==
ISE will do more than is described here. This is just the basic functionality. As I mentioned briefly, you can use the constraints editor to tie a certain signal to a certain pin in order to coordinate with your PCB designer. ISE will generate your programming files (mapping and routing your design onto the selected FPGA) and open up iMPACT, the program which will program your FPGA (or perhaps the [http://en.wikipedia.org/wiki/Programmable_read-only_memory PROM] you attach to your FPGA).