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|+ '''VHDL Tutorial'''

! colspan="2" style="background:#ffff66" | VHDL Tutorial

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| colspan="2" | You are on the index page.

| colspan="2" style="background:#ffff99" | Section three of the tutorial, focusing on coding the body of your design.

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| [[VHDL: Enter the code monkey|< prev]] || [[VHDL: Xilinx ISE|next >]]

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You also see a shorthand that has been pre-defined for you: rising_edge.  There is also falling_edge.  These combine the ''event'' command with a specification of which direction the event happened (transition up or transition down).  Sequential logic makes extensive use of rising_edge and falling_edge.  Also note the else clause.  What is the point of having ''delayed'' loop back on itself?  This is to help the synthesizer along.  VHDL has some quirks and doesn't appreciate an if without an else.  So even if nothing happens, you always want to put that else clause in there and have all the signals in question loop back on themselves.  Otherwise the synthesizer goes crazy and adds latches left and right which at best make your design hideously large and unwieldy and at worst make your design completely nonfunctional.

You also see a shorthand that has been pre-defined for you: rising_edge.  There is also falling_edge.  These combine the ''event'' command with a specification of which direction the event happened (transition up or transition down).  Sequential logic makes extensive use of rising_edge and falling_edge.  Also note the else clause.  What is the point of having ''delayed'' loop back on itself?  This is to help the synthesizer along.  VHDL has some quirks and doesn't appreciate an if without an else.  So even if nothing happens, you always want to put that else clause in there and have all the signals in question loop back on themselves.  Otherwise the synthesizer goes crazy and adds latches left and right which at best make your design hideously large and unwieldy and at worst make your design completely nonfunctional.

Now let's take a look at the second process.

Now let's take a look at the second process.

Here ''i'' is actually a variable (and can be named anything you want it to be named).  However it is a read-only variable, so don't bother trying to write to it.  The bounds of the loop are set by ''a'' and ''b'', which must be static at this point in the program.

Here ''i'' is actually a variable (and can be named anything you want it to be named).  However it is a read-only variable, so don't bother trying to write to it.  The bounds of the loop are set by ''a'' and ''b'', which must be static at this point in the program.

So how are you feeling about all of this code?  Take a look at the other components and see if you can figure out what they're doing as some practice:

So how are you feeling about all of this code?  Take a look at the other components and see if you can figure out what they're doing as some practice.  The files can be found at:

* '''Add a link to DAC_demux.vhd'''

* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/DAC_VHDL.zip DAC files]

* '''Add a link to DAC_follow.vhd'''

* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/Temp_VHDL.zip Temperature sensor files]

* '''Add a link to DAC_hold19.vhd'''

* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip ADC files]

* '''Add a link to DAC_shifter.vhd'''

* '''Add a link to DAC_register.vhd'''

== Putting it together: components ==

== Putting it together: components ==