Changes

Jump to navigation Jump to search
833 bytes added ,  15:05, 17 July 2007
no edit summary
Line 51: Line 51:  
=== The programming cycle ===
 
=== The programming cycle ===
   −
The programming cycle is a conversation intended to set the values of the DAC channels.
+
The programming cycle is a conversation intended to set the values of the DAC channels. It sends programming data to the board and receives confirmation of the programming.
 +
 
 +
==== "P" packet: programming ====
 +
 
 +
This is the packet sent from the PC to the FPGA to set new values to the DAC channels.  The first byte of the packet will be an ASCII '''P''': 0x50, 0101 0000.  The next four bytes (if all 32 channels are used; 2 bytes if 16 channels, 3 if 24 channels) together form a programming mask.  Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 31 (or 23 or 15) and the LSB of the fourth (or third or second) byte will be channel 0.  Thus, if all 32 channels are to be used, but only channels 14 through 26 are to be programmed, the packet would contain:
461

edits

Navigation menu