Changes

Those of you familiar with computer programming may think of this step as "compiling", but since you're not generating an executable file it's not really the same thing.  Synthesis is the step that takes your VHDL code and generates from it a schematic for your circuit.

Those of you familiar with computer programming may think of this step as "compiling", but since you're not generating an executable file it's not really the same thing.  Synthesis is the step that takes your VHDL code and generates from it a schematic for your circuit.

Once you've written your code and are ready to see how the schematic looks, go up to the Sources box and set it as the top module.  And make sure that the file you wish to synthesize is selected.  Then go down to the '''Processes''' box and double click on "Synthesize - XST".  If you do not see that option, then you forgot to set your file as the top module and the Processes box should look something like [[this]].  The User Constraints section allows you to tie certain I/O lines to specific pins on the package.  You can see that in the image Synthesis - XST has a little yellow triangle with an exclamation point next to it.  That means that the design has synthesized with no errors but has warnings.  Double click on "View Synthesis Report" to see any errors and warnings.  Some warnings can safely be ignored, others must be take care of.  An error will generate a red icon.  If ISE is uncertain if the latest version of the file has been synthesized or not, it will place an orange icon with a question mark.  Double clicking Synthesize - XST runs the synthesis, and you can right click and select rerun if you want to be sure the file is up-to-date.

Once you've written your code and are ready to see how the schematic looks, go up to the Sources box and set it as the top module.  And make sure that the file you wish to synthesize is selected.  Then go down to the '''Processes''' box and double click on "Synthesize - XST".  If you do not see that option, then you forgot to set your file as the top module and the Processes box should look something like [[Image:Processes Synthesis-Implementation - non-top module.PNG|this]].  The User Constraints section allows you to tie certain I/O lines to specific pins on the package.  You can see that in the image Synthesis - XST has a little yellow triangle with an exclamation point next to it.  That means that the design has synthesized with no errors but has warnings.  Double click on "View Synthesis Report" to see any errors and warnings.  Some warnings can safely be ignored, others must be take care of.  An error will generate a red icon.  If ISE is uncertain if the latest version of the file has been synthesized or not, it will place an orange icon with a question mark.  Double clicking Synthesize - XST runs the synthesis, and you can right click and select rerun if you want to be sure the file is up-to-date.

[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]

[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]

Once you've synthesized your design, double click on "View RTL Schematic".  RTL stands for Register Transfer Level.  This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together.  As discussed in previous sections, a thick wire is a bus.  By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus.  Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows.  Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows.  Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other.

Once you've synthesized your design, double click on "View RTL Schematic".  RTL stands for Register Transfer Level.  This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together.  As discussed in previous sections, a thick wire is a bus.  By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus.  Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows.  Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows.  Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other.