SiPM digital control board supporting components - Revision history

Underwood: /* LED-less RJ-45 Jack */

2009-11-05T15:16:03Z

LED-less RJ-45 Jack

Underwood: /* XCF01S EEPROM */ added logic levels info

2008-07-22T14:52:35Z

XCF01S EEPROM: added logic levels info

Underwood: /* LED-less RJ-45 Jack */

2008-07-22T14:50:55Z

LED-less RJ-45 Jack

Underwood: /* FPGA/EEPROM Pull-up Resistors */ changed to say they aren't necessary

2008-07-22T14:49:50Z

FPGA/EEPROM Pull-up Resistors: changed to say they aren't necessary

Underwood: /* FPGA Supporting Components */ fixed EEPROM isolating logic section

2008-07-22T14:48:23Z

FPGA Supporting Components: fixed EEPROM isolating logic section

Underwood: SiPM digital control board minor components moved to SiPM digital control board supporting components

2008-06-25T15:37:06Z

SiPM digital control board minor components moved to SiPM digital control board supporting components

Underwood: Added multipurpose components section, and 20MHz crystal oscillator

2008-06-25T15:36:02Z

Added multipurpose components section, and 20MHz crystal oscillator

Underwood: Added CP2201 supporting components section

2008-06-25T15:17:49Z

Added CP2201 supporting components section

Underwood: /* FPGA Supporting Components */ more FPGA supporting components

2008-06-25T15:10:21Z

FPGA Supporting Components: more FPGA supporting components

Underwood: /* XCF01S EEPROM */ added connection diagram for EEPROM

2008-06-25T14:56:03Z

XCF01S EEPROM: added connection diagram for EEPROM

← Older revision		Revision as of 15:16, 5 November 2009
Line 32:		Line 32:
	=== LED-less RJ-45 Jack ===		=== LED-less RJ-45 Jack ===

−	Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. ~~Most likely,~~ we ~~will be using a jack from~~ Pulse Engineering~~, due to their reasonable cost, and large selection~~.	+	Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. The jack we have selected to use on the board is the Pulse Engineering J0012D21.

@@ Line 18: / Line 18: @@
 The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. For more information on the mode of programming the FPGA, see [[FPGA programming modes]].
-TODO: Insert information about logic levels.
+Both the EEPROM and the FPGA are designed to tolerate +3.3V CMOS logic levels, keeping the configuration logic at the same voltages as the other logic on the board.
 === Post-Configuration EEPROM Isolating Logic ===

← Older revision		Revision as of 14:50, 22 July 2008
Line 32:		Line 32:
	=== LED-less RJ-45 Jack ===		=== LED-less RJ-45 Jack ===

−	Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. Most likely, we will ~~want~~ a ~~shielded~~ jack ~~such as the Stewart Connector Systems SS-6488S-A-NF ([http://search.digikey.com/scripts/DkSearch/dksus.dll?pname?site=us;lang=en;name=380-1024-ND Digi-Key Part #380-1024-ND]). However~~, ~~there are many other LED-less jacks available that may also be suitable. For a listing of other LED-less jacks~~, ~~look at the [http://digi-key.dirxion.com/Main.asp?from=emailafriend&pagenav=&bookid=2&pageindex=306 Digi-Key Interactive Catalog]~~.	+	Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. Most likely, we will be using a jack from Pulse Engineering, due to their reasonable cost, and large selection.

@@ Line 26: / Line 26: @@
 === FPGA/EEPROM Pull-up Resistors ===
-As shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif |connection diagram]], 4.7k&Omega; pull-up resistors are necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO.
+Despite being shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif |connection diagram]], 4.7k&Omega; pull-up resistors are not necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO, since we will be enabling internal pull-ups using the PUDC_B pin.
 == CP2201 Ethernet Supporting Components ==

@@ Line 22: / Line 22: @@
 === Post-Configuration EEPROM Isolating Logic ===
-It may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA will be reused as user I/O pins following configuration. Research must be done into whether this logic is necessary. The specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. What is not clear is if changing logic values on the others pins will have an adverse effect when CE is high.
+Originally it was though that it may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA were to be reused as user I/O pins following configuration. However, the specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. We believe this is sufficient to prevent unwanted EEPROM I/O operations due to changing logic levels on its pins following configuration, meaning post-configuration EEPROM isolating logic is not necessary. In addition, due to the large number of available I/O pins on the FPGA, there are sufficient dedicated I/O pins available so that these shared pins do not need to be reused in our design.
 === FPGA/EEPROM Pull-up Resistors ===

← Older revision	Revision as of 15:37, 25 June 2008
(No difference)

← Older revision		Revision as of 15:36, 25 June 2008
Line 2:		Line 2:

	While the FPGA, Ethernet controller, DAC, ADC and Temperature sensor are considered the main components of the SiPM digital control board, there are also many other supporting components that will be on the board. This page discusses many of the other minor components on the SiPM digital control board.		While the FPGA, Ethernet controller, DAC, ADC and Temperature sensor are considered the main components of the SiPM digital control board, there are also many other supporting components that will be on the board. This page discusses many of the other minor components on the SiPM digital control board.
		+
		+	== Multipurpose Supporting Components ==
		+
		+	This section discusses components that function to support two or more of the major components on the control board.
		+
		+	=== 20MHz Crystal Oscillator ===
		+
		+	The SiPM digital control board is driven by a 20MHz clock generated from a crystal oscillator. This signal will be divided into a 5MHz signal by the FPGA for some components, but nonetheless, the 20MHz clock is the main timing signal on the board. The component most sensitive to this signal is the CP2201 Ethernet IC, so the oscillator will be selected to meet the requirements of this chip. According to the [http://www.silabs.com/public/documents/tpub_doc/dsheet/Microcontrollers/Interface/en/CP2200.pdf CP2201 data sheet], the CP2201 requires a 20MHz signal with an error of no more than ±50ppm. One crystal oscillator that meets the requirements of the CP2201 is the Epson Toyocom MA-505 20.0000M-C0 ([http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=SE2509CT-ND Digi-Key Part #SE2509CT-ND]). There are also many other similar oscillators available if the Epson Toyocom model proves insufficient.

	== FPGA Supporting Components ==		== FPGA Supporting Components ==

← Older revision		Revision as of 15:17, 25 June 2008
Line 19:		Line 19:

	As shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif \|connection diagram]], 4.7kΩ pull-up resistors are necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO.		As shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif \|connection diagram]], 4.7kΩ pull-up resistors are necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO.
		+
		+	== CP2201 Ethernet Supporting Components ==
		+
		+	=== LED-less RJ-45 Jack ===
		+
		+	Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. Most likely, we will want a shielded jack such as the Stewart Connector Systems SS-6488S-A-NF ([http://search.digikey.com/scripts/DkSearch/dksus.dll?pname?site=us;lang=en;name=380-1024-ND Digi-Key Part #380-1024-ND]). However, there are many other LED-less jacks available that may also be suitable. For a listing of other LED-less jacks, look at the [http://digi-key.dirxion.com/Main.asp?from=emailafriend&pagenav=&bookid=2&pageindex=306 Digi-Key Interactive Catalog].

@@ Line 7: / Line 7: @@
 === XCF01S EEPROM ===
 The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA.
-TODO: Insert information about logic levels. Insert connection diagram
+TODO: Insert information about logic levels.