SiPM digital control board - Revision history

Senderovich at 01:04, 5 November 2009

2009-11-05T01:04:27Z

Senderovich: /* The FPGA */

2009-11-05T00:54:11Z

The FPGA

Senderovich at 05:41, 29 October 2009

2009-10-29T05:41:54Z

Senderovich at 17:59, 25 September 2009

2009-09-25T17:59:05Z

Underwood: /* Important Links */ added link to prototype notes page

2009-02-23T16:10:22Z

Important Links: added link to prototype notes page

Underwood: /* Important Links */ added link to new parts list page

2008-07-16T13:55:20Z

Important Links: added link to new parts list page

Underwood: /* The components */ modified minor components link to reflect new page name

2008-06-25T19:14:48Z

The components: modified minor components link to reflect new page name

Underwood: /* Important Links */ added link to power supplies page

2008-06-25T15:48:48Z

Important Links: added link to power supplies page

Underwood: /* Important Links */

2008-06-25T15:44:06Z

Important Links

Underwood: added important links section

2008-06-25T15:43:45Z

added important links section

@@ Line 32: / Line 32: @@
 ** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.
 * [[Programming the DAC|Programming the DAC controller]]
 === The Ethernet controller ===
-After researching a variety of communication buses, including USB, I<sup>2</sup>C, FireWire, and various others, it was decided that the best choice would be Ethernet.  Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet.  In addition, due to the wide availability of Ethernet hubs/switches, Ethernet will help to minimize the number of wires that must be run between the control board array and the main computer.
+After researching a variety of communication buses, including USB, I<sup>2</sup>C, FireWire, and various others, it was decided that the best choice would be Ethernet.  Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. The wide availability of Ethernet products is a major advantage of this choice of communication scheme.
-We have selected the Silicon Laboratories CP2200/1 Ethernet controller.  The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA has been designed around this chip.
+We have selected the Silicon Laboratories CP2200/1 Ethernet controller.  The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA firmware has been designed around this chip.
 The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].
 === The DAC ===
-The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs.  For this purpose a DAC is required.  The current design of the tagger microscope calls for 16 SiPMs per electronics card, however designs of up to 24 SiPMs per electronics card are being considered.  Various designs were studied, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535.  It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels.  As there are so many channels built in to this system, the tagger may be slightly restructured so as to include up to 32 SiPMs per board instead of 16 per board.  This DAC defines its own serial interface for communication with the FPGA.
+The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs.  For this purpose a DAC is required.  The current design of the tagger microscope calls for 25 or 30 SiPMs per amplifier board (to read out an entire 5x5 or 5x6 scintillating fiber bundle.) Various designs were studied, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535.  It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels. The chip defines its own serial interface for communication with the FPGA.
 The data sheet and other information regarding the DAC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html Analog Devices website].
 === The ADC ===
@@ Line 51: / Line 54: @@
 [[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]
-In order to monitor the voltage levels of the power lines and possibly some DAC channels, an ADC is to be included in the design.  The Analog Devices' AD7928 is an eight-channel ADC.  Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be.  It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.
+In order to monitor the voltage levels of the power lines, an ADC was included in the design. Additional important uses of the chip is monitoring of a DAC channel for online calibration and temperature measurements of the DAC (integrated diode provided) and the amplifier board via its thermistor.
 The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].
 === Temperature sensor ===
-In order to monitor the ambient temperature, a temperature sensor is to be included in the design.  The Analog Devices' AD7314 has ten-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.
+In order to monitor the ambient temperature, a temperature sensor is to be included in the design.  The Analog Devices' AD7314 has 10-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.
 The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].

@@ Line 23: / Line 23: @@
 [[Image:Spartan.jpg|right]]
-The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. The code for the FPGA has been written in [[VHDL_tutorial|VHDL]] and is in the final stages of debugging. The question as to which size of FPGA to choose from the available 50k-1400k may be settled, as the current design implementation fits within the 50k unit.
+The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. The code for the FPGA, written in [[VHDL_tutorial|VHDL]], is complete. Remaining tweaks are subject to the use experience during beam tests and any other field experience.
 The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].
-Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and SPI (bus for ADC and Temperature sensor) controller modules when access to these chips is required. Please see the relevant pages from the following list.
+Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and the SPI-based ADC and Temperature sensor when access to these chips is required. Please see the relevant pages from the following list.
 * [[Programming the Ethernet controller|Programming the Ethernet controller (core of FPGA design)]]
 ** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.
 * [[Programming the DAC|Programming the DAC controller]]
 === The Ethernet controller ===

@@ Line 1: / Line 1: @@
-The '''SiPM digital control board''' is the communication block for controlling the SiPMs.  It provides the interface through which an external system can control or monitor the SiPMs. Additionally, it serves as an outlet of amplified SiPM signals.
+The '''SiPM digital control board''' provides remote control and monitoring of the SiPM (silicon photomultiplier) electronics. Variation in performance from one SiPM to the next, their temperature sensitivity, variation from one optical channel to the next as well as varying output due to scintillator degradation from radiation calls for active control of individual SiPMs to compensate for adverse effects.
 == Responsibilities of the control board ==
-The control board is responsible for providing a layer of interaction between the researchers running the experiments and the tagger microscope.  The foremost responsibility of the control board is to allow the users to program the bias voltage (which controls the gain) of the SiPMs.  It receives signals from an external PC and communicates that information to a DAC which controls the bias voltage.  It also monitors itself and reports back to the PC certain statistics, such as voltage of the power lines (to ensure the chips and SiPMs are receiving the required voltages) and temperature of the control board and its immediate vicinity (to ensure that the electronics are not overheating).
+The control board is responsible for providing a layer of interaction between the researchers running the experiments and the tagger microscope's SiPM electronics.  The foremost responsibility of the control board is to allow the users to program the SiPM bias voltage, which controls the gain and photo-detection efficiency.  It receives signals from an external PC and communicates that information to a [http://en.wikipedia.org/wiki/Digital-to-analog_converter DAC] which controls the bias voltage.  It also monitors itself and reports back to the PC certain statistics, such as voltage of the power lines (to ensure the chips and SiPMs are receiving the required voltages) and temperature of the control and amplifier boards (to ensure that the electronics are not overheating). Additionally, voltage information read back from the DAC allows for feedback that assists calibration.
-[[Image:Control Board Functional Block.JPG|thumb|Functional Block Diagram]]
+== The Components ==
-The hub of the control board, its "central nervous system", is an [http://en.wikipedia.org/wiki/FPGA FPGA].  All components on the board connect to the FPGA and it coordinates their interactions.  Communication with the outside world (more specifically an external PC) occurs over [http://en.wikipedia.org/wiki/Ethernet Ethernet].  Towards that end an Ethernet chip is included on the board and connected to the FPGA.  The main purpose of the board is to control bias voltages, so a [http://en.wikipedia.org/wiki/Digital-to-analog_converter DAC] is attached to the board and connected to the FPGA.  There are two monitoring devices so that the board can ensure that it is running properly: a temperature sensor and an [http://en.wikipedia.org/wiki/Analog-to-digital_converter ADC], both of which are connected to the FPGA.  The functional block diagram of the board is shown to the right.  Note that communication on the left (to the analog sensor board) is outgoing simplex and communication to the right (to the Ethernet hub) is duplex.
+[[Image:ControlBoard.png|thumb|300px]]
-To better understand the internal flow of information, a netlist of the connections between the components shown in functional block diagram is available here: [[SiPM digital control board netlist]].
+The hub of the control board, its "central nervous system", is an [http://en.wikipedia.org/wiki/FPGA FPGA].  All components on the board connect to the FPGA and it coordinates their interactions.  Communication with the outside world (more specifically an external PC) occurs over [http://en.wikipedia.org/wiki/Ethernet Ethernet]. This was a natural choice, being a robust, long distance, inexpensive communication bus. To implement this, an Ethernet controller chip is included on the board and connected to the FPGA.  There are two monitoring devices so that the board can ensure that it is running properly: a temperature sensor and an [http://en.wikipedia.org/wiki/Analog-to-digital_converter ADC].
-== The components ==
+The adjacent diagram shows the component connection scheme. The dashed horizontal line represents the "backplane" board which interfaces the digital control board with the SiPM amplifier board and seals the latter inside the light-tight microscope enclosure while keeping the control board outside for easy cable connection. As shown, up to 32 voltage lines on the amplifier board may be controlled by the DAC chip chosen of the control board design. In practice, the natural segmentation of the optical channels makes 25 or 30 channels the maximum. Conveniently, the remaining 2 DAC channels are used for [[SiPM_Amplifier_Optimization#The_Gain_Switch|amplifier gain selection]] and for calibration. It is important to note that the Ethernet based control board is not addressed only by its MAC address, but is automatically cross-referenced to its location in the microscope electronics board array. An "Location Stamp" number, jumper-coded into the backplane slot to which the control board is connected clarifies its identity in terms of the microscope energy bins it controls. This significantly simplifies setup, since a once time slot-coding fixes the board address space no matter which generic copy of the control board is inserted.
 === The FPGA ===

@@ Line 61: / Line 61: @@
 The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].
 == Important Links ==
-Here is a summary of important pages relating to the SiPM digital control board.
+Here is a summary of important pages relating to the SiPM digital control board instrumentation.
-[[SiPM digital control board parts list]]
+*[[SiPM digital control board netlist|Netlist]]
 [[SiPM digital control board prototype notes]]

← Older revision		Revision as of 16:10, 23 February 2009
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	[[SiPM digital control board parts list]]		[[SiPM digital control board parts list]]
		+
		+	[[SiPM digital control board prototype notes]]

← Older revision		Revision as of 13:55, 16 July 2008
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	[[SiPM digital control board power supplies]]		[[SiPM digital control board power supplies]]
		+
		+	[[SiPM digital control board parts list]]

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 == The components ==
-Discussed here are the five major components included on the digital control board, not counting interconnect wires, passive components, crystals, etc. Details on these smaller components can be found under [[SiPM digital control board minor components]].
+Discussed here are the five major components included on the digital control board, not counting interconnect wires, passive components, crystals, etc. Details on these smaller components can be found under [[SiPM digital control board supporting components]].
 === The FPGA ===

← Older revision		Revision as of 15:48, 25 June 2008
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	[[FPGA programming modes\|SiPM digital control board FPGA programming modes]]		[[FPGA programming modes\|SiPM digital control board FPGA programming modes]]
		+
		+	[[SiPM digital control board power supplies]]

← Older revision		Revision as of 15:43, 25 June 2008
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	The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].		The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].
		+
		+	== Important Links ==
		+
		+	Here is a summary of important pages relating to the SiPM digital control board.
		+
		+	[[SiPM digital control board netlist]]
		+	[[SiPM digital control board supporting components]]
		+	[[FPGA programming modes\|SiPM digital control board FPGA programming modes]]