FPGA programming modes - Revision history

Underwood: /* Master serial (platform flash) mode */ added brief overview of interface with platform flash chips

2008-06-24T19:25:26Z

Master serial (platform flash) mode: added brief overview of interface with platform flash chips

Underwood: /* Programming Modes */ added justification of master serial mode

2008-06-24T19:14:35Z

Programming Modes: added justification of master serial mode

Underwood: described why we are using master serial mode, added section for it

2008-06-24T19:11:35Z

described why we are using master serial mode, added section for it

Underwood at 18:40, 24 June 2008

2008-06-24T18:40:29Z

Underwood at 16:44, 24 June 2008

2008-06-24T16:44:21Z

New page

The Xilinx Spartan-3A FPGA we will be using on the SiPM control board can be programmed using any of several modes. This table, adapted from the [http://www.xilinx.com/support/documentation/user_guides/ug332.pdf User Guide], Table 2-1, shows the available programming modes and how to select them by setting the M[2:0] pins on the FPGA.

For information about the other pins used in the programming process, see [[SiPM digital control board netlist]].

{| cellspacing=3 border=1 |
|'''M[2:0]'''
|'''Programming Mode'''
|----
|<0:0:0>
|Master serial (platform flash) mode
|----
|<0:0:1>
|Master SPI mode
|----
|<0:1:0>
|BPI up
|----
|<0:1:1>
|''Reserved''
|----
|<1:0:0>
|''Reserved''
|----
|<1:0:1>
|JTAG mode
|----
|<1:1:0>
|Slave parallel mode
|----
|<1:1:1>
|Slave serial mode
|----
|}

← Older revision		Revision as of 19:25, 24 June 2008
Line 36:		Line 36:
	For information about the other pins used in the programming process, see [[SiPM digital control board netlist]].		For information about the other pins used in the programming process, see [[SiPM digital control board netlist]].

−	=== Master serial (~~platform flash~~) mode ===	+	=== Master serial (Platform Flash) mode ===
		+
		+	Operating in master serial mode, the FPGA generates its own clock signal during the programming process. This clock signal is output through the FPGA's CCLK pin (see [[SiPM digital control board netlist#Configuration pins \| FPGA Configuration Pins]]). When used with a compatible [http://www.xilinx.com/products/silicon_solutions/proms/pfp/spartan.htm Xilinx EEPROM], the FPGA can read data from the EEPROM by driving the EEPROM's CE and OE pins high, and waiting for CF to rise. New data is available on the D0 pin a short while after each rising clock edge.

@@ Line 1: / Line 1: @@
 The Xilinx Spartan-3A FPGA we will be using on the SiPM control board can be programmed using any of several modes. This table, adapted from the [http://www.xilinx.com/support/documentation/user_guides/ug332.pdf User Guide], Table 2-1, shows the available programming modes and how to select them by setting the M[2:0] pins on the FPGA.
@@ Line 32: / Line 33: @@
 |----
 |}

@@ Line 2: / Line 2: @@
 The Xilinx Spartan-3A FPGA we will be using on the SiPM control board can be programmed using any of several modes. This table, adapted from the [http://www.xilinx.com/support/documentation/user_guides/ug332.pdf User Guide], Table 2-1, shows the available programming modes and how to select them by setting the M[2:0] pins on the FPGA.
-We will be using the [[#Master serial (platform flash) mode | master serial]] programming mode, since it is simplest to set up, requires fewer pins, and we don't need the higher speed of the a parallel programming mode.
+We will be using the [[#Master serial (platform flash) mode | master serial]] programming mode, since it is simplest to set up, requires fewer pins, and we don't need the higher speeds of the other available modes. For our purposes, reducing the number of pins on the EEPROM and the number of leads on the board is more important than reducing the start-up time of the FPGA.
 {| cellspacing=3 border=1 |
 |'''M[2:0]'''
 |'''Programming Mode'''
-| bgcolor="#33ff33"----
+|----
-|<0:0:0>
+| bgcolor="#99ff99" | <0:0:0>
-|Master serial (platform flash) mode
+| bgcolor="#99ff99" | Master serial (platform flash) mode
 |----
 |<0:0:1>