FPGA Transmitter - Revision history

Senderovich at 06:31, 5 November 2009

2009-11-05T06:31:15Z

Senderovich at 19:51, 3 June 2008

2008-06-03T19:51:08Z

Senderovich at 19:15, 3 June 2008

2008-06-03T19:15:01Z

Senderovich at 19:04, 3 June 2008

2008-06-03T19:04:47Z

Senderovich: /* Programming Details of Rest_hard */

2008-06-03T19:04:03Z

Programming Details of Rest_hard

Senderovich at 18:33, 3 June 2008

2008-06-03T18:33:46Z

Senderovich at 19:05, 16 May 2008

2008-05-16T19:05:43Z

Senderovich at 19:03, 16 May 2008

2008-05-16T19:03:58Z

Senderovich at 18:57, 16 May 2008

2008-05-16T18:57:38Z

New page

== (001) Transmit "I" ==

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

← Older revision		Revision as of 06:31, 5 November 2009
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	The Transmitter is responsible for compiling report packets for sending to the PC. As discussed [[Ethernet packets#"S" packet: status report\|elsewhere]], the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the [[FPGA_Idler\|Idler]] to await the next request from the PC.		The Transmitter is responsible for compiling report packets for sending to the PC. As discussed [[Ethernet packets#"S" packet: status report\|elsewhere]], the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the [[FPGA_Idler\|Idler]] to await the next request from the PC.
		+
		+	Since the time required to compose a packet by this module is about the same as the time to receive a minimum-length packet, the Transmitter temporarily disables the EC's Receiver Interface.

@@ Line 9: / Line 9: @@
 The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the ''RAwrToAddr'' (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored.
@@ Line 32: / Line 34: @@
 [[FPGA_Registers#Temperature Register|Temperature]], [[FPGA_Registers#ADC Registers|ADC]] and [[FPGA_Registers#DAC Registers|DAC]] register control lines
-* ''TempReg_Q'': [in] 16-bit (front-padded 10-bit) Temperature register value
+* ''TempReg_Q'': [in] 16-bit (pre-padded 10-bit) Temperature register value
 * ''ADCReg_Addr'': [out] 3-bit ADC register address
-* ''ADCReg_Q'': [in] 16-bit (front-padded 12-bit) ADC register value
+* ''ADCReg_Q'': [in] 16-bit (pre-padded 12-bit) ADC register value
 * ''DACReg_Addr'': [out] 5-bit DAC register address bus
-* ''DACReg_Q'': [in] 16-bit (front-padded 14-bit) DAC register value
+* ''DACReg_Q'': [in] 16-bit (pre-padded 14-bit) DAC register value
@@ Line 45: / Line 47: @@
 * ''TxRx_Dout'': [out] EC control register write value
 * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]

@@ Line 36: / Line 36: @@
 * ''ADCReg_Q'': [in] 16-bit (front-padded 12-bit) ADC register value
 * ''DACReg_Addr'': [out] 5-bit DAC register address bus
-* ''DACReg_Q : [in] 16-bit (front-padded 14-bit) DAC register value
+* ''DACReg_Q'': [in] 16-bit (front-padded 14-bit) DAC register value

@@ Line 31: / Line 31: @@
-[[FPGA_Registers#Temperature Register|Temperature]], [[FPGA_Registers#ADC Register|ADC]] and [[FPGA_Registers#DAC Register|DAC]] register control lines
+[[FPGA_Registers#Temperature Register|Temperature]], [[FPGA_Registers#ADC Registers|ADC]] and [[FPGA_Registers#DAC Registers|DAC]] register control lines
 * ''TempReg_Q'': [in] 16-bit (front-padded 10-bit) Temperature register value
 * ''ADCReg_Addr'': [out] 3-bit ADC register address
@@ Line 45: / Line 45: @@
 * ''TxRx_Dout'': [out] EC control register write value
 * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]
 == (111) Transmit "D" ==

@@ Line 4: / Line 4: @@
-== Programming Details of Rest_hard ==
+== Programming Details  ==
 The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1.
@@ Line 14: / Line 14: @@
 * ''Clk'': [in] clock
-Reset Signals
+[[FPGA_Registers#Temperature Register|Temperature]], [[FPGA_Registers#ADC Register|ADC]] and [[FPGA_Registers#DAC Register|DAC]] register control lines
-* ''Rst: [in] asynchronous reset
+* ''TempReg_Q'': [in] 16-bit (front-padded 10-bit) Temperature register value
 == (111) Transmit "D" ==

@@ Line 1: / Line 1: @@
-== (101) Transmit "S" ==
+= (1X1) Transmitter =
-This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it.  Once the packet has been sent, the block transitions to state 010.
+The Transmitter is responsible for compiling report packets for sending to the PC. As discussed [[Ethernet packets#"S" packet: status report|elsewhere]], the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the [[FPGA_Idler|Idler]] to await the next request from the PC.
-internal signals
+== Programming Details of Rest_hard ==
-blocks
+The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1.
-* '''Temp Loader'''
-** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
+The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the ''RAwrToAddr'' (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored.
-** inputs
-*** ''Clk'': clock
-*** ''/Rst'': asynchronous, active-low reset
+=== Ports ===
-*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
-*** ''D_in'': 16-bit data bus from internal registers
+* ''Clk'': [in] clock
-*** ''TxRx_Done'': ''Done'' signal from transceiver
-** ouputs
-*** ''TxRx_Go'': ''Go'' signal on transceiver
+Reset Signals
-*** ''TxRx_R/W'': ''R/W'' signal on transceiver
+* ''Rst: [in] asynchronous reset

← Older revision		Revision as of 19:05, 16 May 2008
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	*** ''TxRx_D'': ''D_in'' bus on transceiver		*** ''TxRx_D'': ''D_in'' bus on transceiver
	*** ''Done'': pulse to signal completion		*** ''Done'': pulse to signal completion
		+
		+
		+
		+	== (111) Transmit "D" ==
		+
		+	This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.
		+
		+	inputs
		+	* ''Clk'': clock
		+	* ''/Rst'': asynchronous, active-low reset
		+	* ''State'': 3-bit state value
		+
		+	internal signals
		+	* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
		+	* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
		+
		+	blocks
		+	* '''Loader'''
		+	** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
		+	** inputs
		+	*** ''Clk'': clock
		+	*** ''/Rst'': asynchronous, active-low reset
		+	*** ''Go'': pulse to begin loading a packet
		+	*** ''TxRx_Done'': ''Done'' signal on transceiver
		+	*** ''Data'': 14-bit data bus from internal registers
		+	** outputs
		+	*** ''TxRx_Go'': ''Go'' signal on transceiver
		+	*** ''TxRx_RW'': ''R/W'' signal on transceiver
		+	*** ''TxRx_A'': ''A_in'' bus on transceiver
		+	*** ''TxRx_D'': ''D_in'' bus on transceiver
		+	*** ''Done'': pulse to signal completion
		+	* '''Sender'''
		+	** Tells CP2200/1 to send the packet
		+	** inputs
		+	*** ''Clk'': clock
		+	*** ''/Rst'': asynchronous, active-low reset
		+	*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
		+	*** ''TxRx_Done'': ''Done'' signal from transceiver
		+	** outputs
		+	*** ''TxRx_Go'': ''Go'' signal on transceiver
		+	*** ''TxRx_RW'': ''R/W'' signal on transceiver
		+	*** ''TxRx_A'': ''A_in'' bus on transceiver
		+	*** ''TxRx_D'': ''D_in'' bus on transceiver
		+	*** ''Done'': pulse to signal completion
		+	*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

@@ Line 1: / Line 1: @@
-== (001) Transmit "I" ==
+== (101) Transmit "S" ==
-This is a simple state.  It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding).  After the transmission is complete, the block writes a 010 to the state register.
+This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it.  Once the packet has been sent, the block transitions to state 010.
 inputs
@@ Line 9: / Line 9: @@
 internal signals
-* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
+* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
 * ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
 blocks
-* '''Transmitter'''
+* '''Temp Loader'''
-** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
+** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
 ** inputs
 *** ''Clk'': clock
 *** ''/Rst'': asynchronous, active-low reset
-*** ''Go'': pulse to begin sending
+*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
-*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
+*** ''D_in'': 16-bit data bus from internal registers
 ** outputs
-*** ''TxRx_A'': ''A_in'' signal to transceiver
+*** ''TxRx_Go'': ''Go'' signal on transceiver
-*** ''TxRx_D'': ''D_in'' signal to transceiver
+*** ''TxRx_R/W'': ''R/W'' signal on transceiver
-*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
+*** ''TxRx_A'': ''A_in'' bus on transceiver
-*** ''TxRx_Go'': ''Go'' signal to transceiver
+*** ''TxRx_D'': ''D_in'' bus on transceiver
-*** ''Done'': pulses for one cycle; connects to state register as an enable line
+*** ''Done'': pulse to signal completion