FPGA Registers - Revision history

Senderovich at 19:20, 4 June 2009

2009-06-04T19:20:17Z

Senderovich: /* State Register */

2009-06-04T19:19:34Z

State Register

Senderovich: /* DAC Registers */

2009-06-04T19:19:05Z

DAC Registers

Senderovich at 23:41, 6 June 2008

2008-06-06T23:41:10Z

Senderovich at 23:37, 6 June 2008

2008-06-06T23:37:27Z

Senderovich at 19:45, 3 June 2008

2008-06-03T19:45:58Z

Senderovich at 18:54, 16 May 2008

2008-05-16T18:54:46Z

New page

= Registers =

=== State Register ===
A three-bit register to store the current state.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''D'': three-bit data-in bus

outputs
* ''Q'': three-bit data-out bus

=== Packet Type Register ===
An 8-bit register to store the 2nd byte of an accepted packet.
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''D'': 8-bit data-in bus

outputs
* ''Q'': 8-bit data-out bus

=== Temperature Register ===
A 16-bit register to store the most recent temperature data.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''D'': 10-bit data-in bus

outputs
* ''Q'': 16-bit data-out bus (data pre-padded with 6 zeros to facilitate packaging into 2-byte words)

=== ADC Registers ===
A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''A'': 3-bit address
* ''D'': 12-bit data-in bus

outputs
* ''Q'': 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)

=== DAC Registers ===
A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
* ''En'': write enable
* ''A'': 5/5/4-bit address (currently set at 5-bit)
* ''D'': 14-bit data-in bus

outputs
* ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)

@@ Line 1: / Line 1: @@
 === State Register ===
 A three-bit register to store the current state.
@@ Line 10: / Line 11: @@
 outputs
 * ''Q'': three-bit data-out bus
 === MAC Address Registers ===
@@ Line 56: / Line 58: @@
 === DAC Registers ===
 A set of 32 14-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules.

@@ Line 13: / Line 13: @@
 === MAC Address Registers ===
-A set of eight 12-bit registers to store the most recent ADC data.  Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules.
+A set of 12 8-bit registers to store the board's and PC's MAC addresses (in that order). Note that all bits of the register are set high upon reset as a simple way to ensure that packets sent to the PC before its address has been learned will be interpreted as a broadcast packet.
 inputs

@@ Line 1: / Line 1: @@
 === State Register ===
 A three-bit register to store the current state.
@@ Line 13: / Line 11: @@
-=== Packet Type Register ===
+=== MAC Address Registers ===
-An 8-bit register to store the 2nd byte of an accepted packet.
 inputs
 * ''Clk'': clock
 * ''Rst'': asynchronous reset to zero the register
 * ''En'': write enable
-* ''D'': 8-bit data-in bus
+* ''A'': 3-bit address
 outputs
-* ''Q'': 8-bit data-out bus
+* ''Q'': 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)
 === Temperature Register ===
-A 16-bit register to store the most recent temperature data.
 inputs
 * ''Clk'': clock
@@ Line 38: / Line 41: @@
 === ADC Registers ===
-A set of eight 16-bit registers to store the most recent ADC data.  Also includes a demultiplexer to select which register to write to.
 inputs
 * ''Clk'': clock
@@ Line 51: / Line 56: @@
 === DAC Registers ===
-A set of 32 16-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to.
+A set of 32 14-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules.
 inputs
 * ''Clk'': clock