FPGA Idler - Revision history

Senderovich at 00:15, 3 June 2008

2008-06-03T00:15:26Z

Senderovich at 00:14, 3 June 2008

2008-06-03T00:14:28Z

Senderovich at 18:25, 2 June 2008

2008-06-02T18:25:18Z

Senderovich at 20:37, 30 May 2008

2008-05-30T20:37:21Z

Senderovich at 18:58, 16 May 2008

2008-05-16T18:58:53Z

New page

== (010) Idle ==

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''state_in'': 3-bit state value

* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete
* ''TxRx_Go'': transceiver go line
* ''TxRx_R/W'': read/write flag for transceiver
* ''TxRx_Aout'': register address bus for transceiver

blocks
* '''Request INT0RD''' (0x76) register via <tt>reqFromAddr</tt> pulsed by the ''LoopEn'' signal from Looper (below).
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''LoopEn'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

← Older revision		Revision as of 00:15, 3 June 2008
Line 1:		Line 1:
−	:''See also [[Programming_the_Ethernet_controller\|Programming the Ethernet Controller]]'' for a survey of modules and general discussion of FPGA design approach.''	+	:''See also [[Programming_the_Ethernet_controller\|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''

	= (010) Idler =		= (010) Idler =

@@ Line 1: / Line 1: @@
 = (010) Idler =
@@ Line 5: / Line 7: @@
 == Programming Details ==
 === Ports ===

@@ Line 19: / Line 19: @@
 * ''TxRx_Go'': [out] "Go" signal to read an EC control register byte
 * ''TxRX_RiW'': [out] active-high read, active-low write flag
-* ''TxRx_Aout'': [out]  _VECTOR (7 downto 0);
+* ''TxRx_Aout'': [out] EC control register address (8-bit)

@@ Line 1: / Line 1: @@
-== (010) Idle ==
+= (010) Idler =
-Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero.  On this condition it transitions to state 011.
+The Idler Block corresponding to state 010 continuously is the default module running an "idle process". It awaits an interrupt corresponding to "Receive FIFO non-empty", unpon which it transitions to state 011 - [[FPGA_Reader|Read]].
-* ''TxRx_D'': 8-bit data from transceiver
+== Programming Details ==
-blocks
+* ''Clk'': [in] clock
-* '''Request INT0RD''' (0x76) register via <tt>reqFromAddr</tt> pulsed by the ''LoopEn'' signal from Looper (below).
+* ''Rst: [in] asynchronous reset
-* '''Looper'''
-** Switch to determine if this state should loop on itself or continue to the next state.
+* ''Eth_iINT'': [in] EC interrupt pin
-** inputs
+* ''state_in'': [in] 3-bit FPGA state value
-*** ''S_En'': state enable
-*** ''TxRx_Done'': ''Done'' pulse from transceiver
+[[FPGA_Transceiver|Transceiver]] Control Lines
-*** ''TxRx_Data'': ''D_out'' bus from transceiver
+* ''TxRx_Din'': [in]  EC control register return value
-** outputs
+* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
-*** ''LoopEn'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
+* ''TxRx_Go'': [out] "Go" signal to read an EC control register byte
-*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
+* ''TxRX_RiW'': [out] active-high read, active-low write flag
-*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high
+* ''TxRx_Aout'': [out]  _VECTOR (7 downto 0);