Ethernet packets - Revision history

Senderovich: /* The query cycle - "Q" packet */

2009-12-15T16:43:13Z

The query cycle - "Q" packet

Fowler at 22:40, 10 December 2009

2009-12-10T22:40:48Z

Senderovich at 19:27, 5 November 2009

2009-11-05T19:27:48Z

Senderovich at 18:56, 5 November 2009

2009-11-05T18:56:26Z

Senderovich at 18:54, 5 November 2009

2009-11-05T18:54:59Z

Senderovich: /* "D" packet: DAC setup complete */

2009-11-05T06:31:38Z

"D" packet: DAC setup complete

Senderovich at 05:55, 5 November 2009

2009-11-05T05:55:49Z

Senderovich at 04:44, 5 November 2009

2009-11-05T04:44:14Z

Senderovich at 04:21, 5 November 2009

2009-11-05T04:21:10Z

Senderovich: /* Packets from the PC to the FPGA */

2009-11-05T01:17:29Z

Packets from the PC to the FPGA

@@ Line 47: / Line 47: @@
 The query cycle is a conversation regarding the status of the digital board.  It polls the sensor devices and reports back their most recent data.
-The Q-packet is sent from the PC to the FPGA to request a status report from its sensor chips. There is no data attached to a query packet: the FPGA triggers the [[FPGA_Querier|query module]] upon recognizing a Q-type packet, which is identified as ASCII '''Q''': 0x51, 0101 0001 in the packet type field (2nd byte of packet payload). The boards reports back in response to the query via the [[Ethernet_packets#"S" packet: status report|S-packet]].
+The Q-packet is sent from the PC to the FPGA to request a status report from its sensor chips. There is no data attached to a query packet: the FPGA triggers the [[FPGA_Querier|query module]] upon recognizing a Q-type packet, which is identified as ASCII '''Q''': 0x51, 0101 0001 in the packet type field (2nd byte of packet payload). The board reports back in response to the query via the [[Ethernet_packets#"S" packet: status report|S-packet]].
 === The programming cycle - "P" Packet===

@@ Line 90: / Line 90: @@
 === "D" packet: DAC setup complete ===
-This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels printed in 2-byte words.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Thus PC software needing to rebuild its records of voltage values can issue a program (P) packet with the mask bits set to zero to read back the SiPM bias voltages from the control board.
+This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first two bytes of the packet will be the usual Location Stamp byte and the packet identifier: an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels printed in 2-byte words.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Thus PC software needing to rebuild its records of voltage values can issue a program (P) packet with the mask bits set to zero to read back the SiPM bias voltages from the control board.
 Note that the DAC chip has a write-only interface: state of particular channels cannot be queried. The returned voltages are those stored by the FPGA for programming. The values reported are the nominal programmed values simply confirming that the correct values were received. However, the returned values do reflect the corrections made by the FPGA in the values that would have exceeded the voltage limits.

@@ Line 73: / Line 73: @@
 <math>V=50 V_{ref}\frac{D}{2^{14}}</math>
-where D is the 14-bit binary representation of the voltage value and <math>V_{ref}=3.3V</math> in the current board design, yielding a 0-165V range, assuming the recommended <math>10V+V_{max}=175V</math> power supply is used.
+where D is the 14-bit binary representation of the voltage value and V<sub>ref</sub>=3.3V in the current board design, yielding a 0-165V range, assuming the recommended 10V+V<sub>max</sub>=175V power supply is used.
 Place holders for all channels must be present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  Regardless of the mask, the word corresponding to the ''last channel must be followed but another byte as padding.'' The packet format is shown in detail in the adjacent figure.

@@ Line 70: / Line 70: @@
 |}
 Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. The nominal transfer function of the DAC chip is:
-<math>V=50*V_{ref}\frac{D}{2^{14}}</math>
-where D is the 14-bit binary representation of the voltage value and <math>V_{ref}=3.3V</math> in the current board design, yielding a 0-165V range, assuming the recommended <math>10V+V_{max}=175V<math> power supply is used.
+<math>V=50 V_{ref}\frac{D}{2^{14}}</math>
 Place holders for all channels must be present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  Regardless of the mask, the word corresponding to the ''last channel must be followed but another byte as padding.'' The packet format is shown in detail in the adjacent figure.

@@ Line 69: / Line 69: @@
 | 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0
 |}
-Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  Place holders for all channels must be present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  Regardless of the mask, the word corresponding to the ''last channel must be followed but another byte as padding.'' The packet format is shown in detail in the adjacent figure.
+Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. The nominal transfer function of the DAC chip is:
@@ Line 90: / Line 94: @@
 For real feedback, the "DAC health channel" may be used instead. The current control board hardware design specifies that DAC channel 31 be used as a DAC-health monitoring level. The line is connected with ADC channel 7. Assignment and reading back of values on this channel will be of great help in calibrating the DAC chip.
-Channel ?? also has a special allocation: it controls the gain switch on the amplifier board.
+Channel 18 also has a special allocation: it controls the gain switch on the amplifier board.

← Older revision		Revision as of 06:31, 5 November 2009
Line 90:		Line 90:
	For real feedback, the "DAC health channel" may be used instead. The current control board hardware design specifies that DAC channel 31 be used as a DAC-health monitoring level. The line is connected with ADC channel 7. Assignment and reading back of values on this channel will be of great help in calibrating the DAC chip.		For real feedback, the "DAC health channel" may be used instead. The current control board hardware design specifies that DAC channel 31 be used as a DAC-health monitoring level. The line is connected with ADC channel 7. Assignment and reading back of values on this channel will be of great help in calibrating the DAC chip.

−	Channel ?? also has a special allocation: it ~~control~~ the gain switch on the amplifier board.	+	Channel ?? also has a special allocation: it controls the gain switch on the amplifier board.

@@ Line 8: / Line 8: @@
 === Transmitting ===
-To the right is a diagram depicting the structure of an Ethernet packet.  On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1.  The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them.  The first significant block is the 6-byte destination MAC address.  The FPGA will have to store this to know the address of its conversation partnet. The next block is the 6-byte source MAC address.  Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address.  This address must be retrieved at start-up, inserted in the MAC interface of the CP2200/1 as well as stored by the FPGA for packet addressing. The next block is the 2-byte length block.  This is the number of bytes of data, i.e. everything between the length block and the CRC.  Then finally comes the data block, which must be padded to a minimum of 46 bytes but cannot exceed 1,500 bytes. In practice, out packets are padded to 47 bytes of payload: ''the letter'' of the CP2200/1 manual seems to indicate although this is likely a mistake. (Their likely error reduces to the fact that N-member array with first index 0 ends with index N-1, not N.)
+To the right is a diagram depicting the structure of an Ethernet packet.  On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1.  The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them.  The first significant block is the 6-byte destination MAC address.  The FPGA will have to store this to know the address of its conversation partnet. The next block is the 6-byte source MAC address.  Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address.  This address must be retrieved at start-up, inserted in the MAC interface of the CP2200/1 as well as stored by the FPGA for packet addressing. The next block is the 2-byte length block.  This is the number of bytes of data, i.e. everything between the length block and the CRC.  Then finally comes the data block, which must be padded to a minimum of 46 bytes but cannot exceed 1,500 bytes. In practice, out packets are padded to 47 bytes of payload: ''the letter'' of the CP2200/1 manual seems to indicate although this is likely a mistake. (Their likely error reduces to the fact that an N-member array with first index 0 ends with index N-1, not N.)
@@ Line 55: / Line 55: @@
 The identifying (second) byte of this packet's payload is ASCII '''P''': 0x50, 0101 0000.  The next four bytes form a programming mask.  Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte refers to channel 0 and the LSB of the fourth byte will be channel 31.  Thus, if only channels 5 through 17 are to be programmed, the packet would contain:
-[[Image:P-packetPayload.png|thumb|399px|P-type packet format]]
+[[Image:P-packetPayload.png|thumb|348px|P-type packet format]]
 {| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
 ! First data byte
@@ Line 69: / Line 69: @@
 | 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0
 |}
-Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  Place holders for all channels must be present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  Regardless of the mask, the word corresponding to the ''last channel must be followed but another byte as padding.''
+Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  Place holders for all channels must be present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  Regardless of the mask, the word corresponding to the ''last channel must be followed but another byte as padding.'' The packet format is shown in detail in the adjacent figure.
@@ Line 76: / Line 76: @@
 === "S" packet: status report ===
-This is the packet sent from the FPGA to the PC to report on the current status of the board.  The first two bytes of the packet will be the usual Location-stamp byte and the packet identifier: an ASCII '''S''': 0x53, 0101 0011.  After that will come the status data.
+This is the packet sent from the control board to the PC to report on the current status of the board.  The first two bytes of the packet will be the usual Location Stamp byte and the packet identifier: an ASCII '''S''': 0x53, 0101 0011.  After that will come the status data.
 * The first two bytes of data will be the temperature. The temperature sensor returns 10 bits of data.  The first byte will contain six leading zeros, then the two MSB of data.  The second byte will contain the 8 LSB of data.
-* The next 16 bytes of data will be the ADC channels.  The ADC returns 8 channels of 12 bits each.  The first byte for each channel will have four leading zeros, then the 4 MSB of the data.  The second byte for each channel will contain the 8 LSB of the data.  The channels will be reported from channel zero to channel seven.
+* The next 16 bytes of data will be the ADC channels.  The 12-bit values returned by the ADC are padded into 2-byte words.  The first byte for each channel will have four leading zeros, then the 4 MSB of the data.  The second byte for each channel will contain the 8 LSB of the data.  The channels will be ''reported from channel seven down to channel zero''.
-This totals 20 bytes: one for Location, one for Packet Type, two of temperature, sixteen of voltages.
+This totals 20 bytes: one for Location, one for Packet Type, two of temperature, sixteen of voltages. In an effort to pad the packet to the minimum size required by Ethernet standards, the temperature and ADC data values in the S-packet may be repeated again in the same sequence.
 === "D" packet: DAC setup complete ===
-This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Note that the DAC chip has no interface for querying the state of particular channels. The values reported are the nominal programmed values simply confirming that the correct values were received. If there remain free ADC channels, they can perhaps be wired to sample some DAC lines in order to have some real confirmation.
+This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels printed in 2-byte words.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Thus PC software needing to rebuild its records of voltage values can issue a program (P) packet with the mask bits set to zero to read back the SiPM bias voltages from the control board.

@@ Line 8: / Line 8: @@
 === Transmitting ===
-To the right is a diagram depicting the structure of an Ethernet packet.  On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1.  The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them.  The first significant block is the 6-byte destination MAC address.  The FPGA will have to store this to know the address of its conversation partnet. The next block is the 6-byte source MAC address.  Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address.  This address must be retrieved at startup, insterted in the MAC interface of the CP2200/1 as well as stored by the FPGA for packet addressing. The next block is the 2-byte length block.  This is the number of bytes of data, i.e. everything between the length block and the CRC.  Then finally comes the data block, which must be padded to a minimum of 46 bytes but cannot exceed 1,500 bytes. In practice, out packets are padded to 47 bytes of payload: ''the letter'' of the CP2200/1 manual seems to indicate although this is likely a mistake. (Their likely error reduces to the fact that N-member array with first index 0 ends with index N-1, not N.)
+To the right is a diagram depicting the structure of an Ethernet packet.  On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1.  The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them.  The first significant block is the 6-byte destination MAC address.  The FPGA will have to store this to know the address of its conversation partnet. The next block is the 6-byte source MAC address.  Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address.  This address must be retrieved at start-up, inserted in the MAC interface of the CP2200/1 as well as stored by the FPGA for packet addressing. The next block is the 2-byte length block.  This is the number of bytes of data, i.e. everything between the length block and the CRC.  Then finally comes the data block, which must be padded to a minimum of 46 bytes but cannot exceed 1,500 bytes. In practice, out packets are padded to 47 bytes of payload: ''the letter'' of the CP2200/1 manual seems to indicate although this is likely a mistake. (Their likely error reduces to the fact that N-member array with first index 0 ends with index N-1, not N.)
@@ Line 33: / Line 33: @@
-===== R-packet - hard reset =====
+==== R-packet - hard reset ====
 The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC), loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).
-===== R'-packet - soft reset =====
+==== R'-packet - soft reset ====
 === The query cycle - "Q" packet ===
@@ Line 69: / Line 70: @@
 |}
 Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  The total size of the data in a programming packet is:
 == Packets from the FPGA to the PC ==

@@ Line 17: / Line 17: @@
 == Packets from the PC to the FPGA ==
-We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle.  Each packet's data section will begin with a single-byte code to identify the packet type.  As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.
+We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle.  Each packet's data section will begin with a two-byte code to identify the relevant board and packet type.  As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.
@@ Line 30: / Line 30: @@
 The "R group" of packets sent from the PC to the card to initiate a reset process in various forms.  Two possible reset packets (corresponding to two degrees of reset) are possible
 * Full or "Hard" reset: This resets all chips on the board. This will contain no data as no further instructions can be remembered after a board reset.
-* Selective or "Soft" reset: This will have flags to reset the Ethernet chip, the ADC/Temperature sensor group (SPI bus), and the DAC.
+* Selective or "Soft" reset: This will have flags to reset the ADC and the DAC. A Soft Reset command also finalizes a Hard Reset cycle, as it allows the control board to learn the PC's MAC address. (Subsequent unicast communication makes for a cleaner system compared to an all-broadcast scheme)
 ===== R-packet - hard reset =====
-The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC) loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).
+The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC), loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).
 ===== R'-packet - soft reset =====
-The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.
+The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a reset mask for the on-board chips. Currently the two least significant bits of this byte order reset of the ADC bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.
 === The query cycle - "Q" packet ===