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= Physical Setup =
= Current Guide to Flashing the Final Production FPGAs =
==Physical Setup ==
*Use the [http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm red Xilinx USB cable box] to connect the digital control board to the computer
*When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
*When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming
== Xilinx Software ==
We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
=== Flashing the Program ===
#Open the Project Navigator
##On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
#If the project doesn't load automatically, load the project file Device.xise
##Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
##FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
#Edit any source files using Vim outside of the Xilinx software
#Right click in the bottom left window on Configure Test Device and select "Rerun All"
##This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
#Run Generate Target PROM/ACE File
#Run Manage Configuration Project (iMPACT)
##This will open up the iMPACT program
##Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
##In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
##TDI should connect to xcf01s_vo20 with the file device.mcs underneath
##The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
#In iMPACT in the top left window click on Create PROM File
##This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
##In the window titled "iMPACT Processes" run Generate File
##When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
#Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
#Click on Program in the iMPACT Processes window
##This should erase any previous programming and flash the new program onto the FPGA
= Igor's Guide to Flashing the First Prototype FPGA =
== Physical Setup ==
*Use the red Xilinx USB cable box to connect the digital control board to the computer.
*Use the red Xilinx USB cable box to connect the digital control board to the computer.
*The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
*The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
*2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
*2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
= Xilinx Software =
== Xilinx Software ==
We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
== Editing the uParam program ==
=== Editing the uParam program ===
*Open Xilinx ISE Project Manager
*Open Xilinx ISE Project Manager
*In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
*In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
*There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
*There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
== Flashing the program ==
=== Flashing the program ===
*Now that the program has been changed and saved, open the Xilinx IMPACT program.
*Now that the program has been changed and saved, open the Xilinx IMPACT program.
*Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
*Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date