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486 bytes removed ,  02:27, 5 December 2013
Line 63: Line 63:  
#*maximum noise P-P 5mV @ 1kHz < f < 5MHz
 
#*maximum noise P-P 5mV @ 1kHz < f < 5MHz
 
#*maximum HF noise P-P 20mV @ f > 5MHz
 
#*maximum HF noise P-P 20mV @ f > 5MHz
#*long-term variation < &pm;50 mV
+
#*long-term variation < &plusmn;10 mV
 
# +5V for cmos logic VCC
 
# +5V for cmos logic VCC
 
#*fixed 4.95V - 5.05V, no adjustment required
 
#*fixed 4.95V - 5.05V, no adjustment required
#*
+
#*#*maximum current 3A (15W power)
   −
 
+
The ripple specs for the 100V and the 6V power supplies are based on the two coupling curves shown below, for coupling from Vbias (top plot) and preamp VCC (bottom plot) into the output signal.
The accuracy for each of these channels should be 0.02%
  −
 
  −
The power required for each of these channels is as follows:
  −
*100V: 1W total for the 34 boards x 15 channels/board (assuming 1uA/SiPM)
  −
*10V: 40W total for all of the boards
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*5V/10V: 15W total for all of the boards
  −
 
  −
The ripple for 0.1Hz-10Hz can be 10mV and for 10Hz-20MHz the ripple should be around 5mV. These values are based on the gain curve below and the requirement that the time scale of the ripple be less than 50ps. Converting to voltage from picoseconds can be done using a linear approximation of the rising edge of a typical pulse (300mV peak height, ~2ns rise time). The spec for the 10Hz-20MHz range is set by the gain curve peak around 60kHz.
      
[[file:FinalPreampVpowerGainCurve.png]]
 
[[file:FinalPreampVpowerGainCurve.png]]

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