Changes

=== "D" packet: DAC setup complete ===

=== "D" packet: DAC setup complete ===

This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels printed in 2-byte words.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Thus PC software needing to rebuild its records of voltage values can issue a program (P) packet with the mask bits set to zero to read back the SiPM bias voltages from the control board.

This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first two bytes of the packet will be the usual Location Stamp byte and the packet identifier: an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels printed in 2-byte words.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Thus PC software needing to rebuild its records of voltage values can issue a program (P) packet with the mask bits set to zero to read back the SiPM bias voltages from the control board.

Note that the DAC chip has a write-only interface: state of particular channels cannot be queried. The returned voltages are those stored by the FPGA for programming. The values reported are the nominal programmed values simply confirming that the correct values were received. However, the returned values do reflect the corrections made by the FPGA in the values that would have exceeded the voltage limits.  

Note that the DAC chip has a write-only interface: state of particular channels cannot be queried. The returned voltages are those stored by the FPGA for programming. The values reported are the nominal programmed values simply confirming that the correct values were received. However, the returned values do reflect the corrections made by the FPGA in the values that would have exceeded the voltage limits.