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SiPM Amplifier Optimization (view source)
Revision as of 20:50, 4 February 2009
, 20:50, 4 February 2009no edit summary
== Design Implementation ==
== Design Implementation ==
The initial approach to this problem of gain switching was just that suggested by Photonique documentation: turning up the amplifier supply voltage. With the transistors' maximal voltage rating of 15 V taken as the high gain setting, some simulations were done to assess the amplifier performance. The following problems were found in this approach:
The initial approach to this problem of gain switching was just that suggested by Photonique documentation: turning up the amplifier supply voltage. With the transistors' maximal voltage rating of 15 V taken as the high gain setting, some simulations were done to assess the amplifier performance. The following problems were found in this approach:
A low-impedance input stage was designed to alleviate the last issue, but the rest remained serious concerns and challenges. An alternate design was adapted in which the supply voltage remains constant but the summing stage offers additional amplification. Gain selection is accomplished with a FET switch, effectively altering the resistance in a transistor stage similar to the common emitter amplifier.
A low-impedance input stage was designed to alleviate the last issue, but the rest remained serious concerns and challenges. An alternate design was adapted in which the supply voltage remains constant but the summing stage offers additional amplification. Gain selection is accomplished with a FET switch, effectively altering the resistance in a transistor stage similar to the common emitter amplifier.
The low impedance input stage was retained from the earlier design and applied the the summing circuit, since it pools currents from the individual amplifiers. In Photonique's design, the input signal sees the transistor base, base-biasing resistor, and a feedback resistor in parallel. The new input stages take the signal on the emitter (base held at a set DC value), in which case the signal sees the emitter resistor and the impedance looking into the emitter in parallel with each other. The latter dominates with an effective resistance of order 25 Ω. The input stages are biased with generous amount of current to keep this value low.
The low impedance input stage was retained from the earlier design and applied the the summing circuit, since it pools currents from the individual amplifiers. In Photonique's design, the input signal sees the transistor base, base-biasing resistor, and a feedback resistor in parallel. The new input stages take the signal on the emitter (base held at a set DC value), in which case the signal sees the emitter resistor and the impedance looking into the emitter in parallel with each other. The latter dominates with an effective resistance of order 25 Ω. The input stages are biased with generous amount of current to keep this value low.
There turned out to be a significant trade-off between gain achieved in the first amplification stage and β sensitivity. Since the variation in beta is cumulative in the progress of the signal through the amplifier, it is essential to keep the variation low at this point. For this reason, the gain has been turned down to around 400 Ω - well below the requirement set by the gain/dynamic range considerations themselves. This stage also draws significant current, accounting for about half the amplifier power budget, to keep this point minimally β-dependent.
There turned out to be a significant trade-off between gain achieved in the first amplification stage and β sensitivity. Since the variation in beta is cumulative in the progress of the signal through the amplifier, it is essential to keep the variation low at this point. For this reason, the gain has been turned down to around 400 Ω - well below the requirement set by the gain/dynamic range considerations themselves. This stage also draws significant current, accounting for about half the amplifier power budget, to keep this point minimally β-dependent.
To keep single channel and summing circuit readout independent of each other, a separate driver for the summing circuit was added. The first stage of the amplifier contains a switchable collector resistance which, the ratio of which with the effective resistance of the driver sets the additional gain sought at this stage. The additional inversion (to a positive-going signal) must be countered with another inverter, followed by the voltage buffer similar to that at the end of the single channel amplifier circuit.
To keep single channel and summing circuit readout independent of each other, a separate driver for the summing circuit was added. The first stage of the amplifier contains a switchable collector resistance which, the ratio of which with the effective resistance of the driver sets the additional gain sought at this stage. The additional inversion (to a positive-going signal) must be countered with another inverter, followed by the voltage buffer similar to that at the end of the single channel amplifier circuit.
Signal buffering turns out to be tricky in this project. The requirement of negative output pulse polarity set by the ADC mandates a PNP transistor for the final stages of both amplifier and summing segments. However, the β characteristics of the only acceptable fast PNP found on the market (BFT92W) are even worse than those in its NPN counterpart. The typical value of <math>h_{FE}</math> is 50 with a minimum value of 20, compared to BFR92P from Infineon, which sports values from 70 to near 100. The effective load of the terminators of about β50 &Omega remains comparable to the source impedance of the circuit. In other words, the source impedance cannot be considered negligible compared to the load, creating an effective voltage divider whose ration depends on beta! Since the output from the summing circuit suffers from about twice as much variation due to β because of all the preceding stages, a stiffer buffer became essential on this end. The emitter-follower driver was doubled, effectively multiply the β's of the two transistors. The resulting two diode drops, too low to avoid significant saturation on collectors of earlier stages, are countered with a DC level shift with AC coupling from preceding circuit elements.
Signal buffering turns out to be tricky in this project. The requirement of negative output pulse polarity set by the ADC mandates a PNP transistor for the final stages of both amplifier and summing segments. However, the β characteristics of the only acceptable fast PNP found on the market (BFT92W) are even worse than those in its NPN counterpart. The typical value of <math>h_{FE}</math> is 50 with a minimum value of 20, compared to BFR92P from Infineon, which sports values from 70 to near 100. The effective load of the terminators of about β50 &Omega remains comparable to the source impedance of the circuit. In other words, the source impedance cannot be considered negligible compared to the load, creating an effective voltage divider whose ration depends on beta! Since the output from the summing circuit suffers from about twice as much variation due to β because of all the preceding stages, a stiffer buffer became essential on this end. The emitter-follower driver was doubled, effectively multiply the β's of the two transistors. The resulting two diode drops, too low to avoid significant saturation on collectors of earlier stages, are countered with a DC level shift with AC coupling from preceding circuit elements.
[[Image:AmpVis_v6_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and Ω are implied unless a different multiple is specified.]]
[[Image:AmpVis_v6_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and Ω are implied unless corrected by different prefix.]]
==== The Gain Switch ====
==== The gain switch ====
A MOSFET switch the effective collector resistor in the first stage of the summing circuit between about 3 kΩ due to R<sub>e</sub> alone and the parallel path of 165 Ω. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3 V (max: -4 V). Putting its source on the supply rail and switching the gate between 5 V (on) and 0 V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.
A MOSFET switch the effective collector resistor in the first stage of the summing circuit between about 3 kΩ due to R<sub>e</sub> alone and the parallel path of 165 Ω. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3 V (max: -4 V). Putting its source on the supply rail and switching the gate between 5 V (on) and 0 V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.