Changes

=== Post-Configuration EEPROM Isolating Logic ===

=== Post-Configuration EEPROM Isolating Logic ===

It may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA will be reused as user I/O pins following configuration. Research must be done into whether this logic is necessary. The specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. What is not clear is if changing logic values on the others pins will have an adverse effect when CE is high.

Originally it was though that it may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA were to be reused as user I/O pins following configuration. However, the specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. We believe this is sufficient to prevent unwanted EEPROM I/O operations due to changing logic levels on its pins following configuration, meaning post-configuration EEPROM isolating logic is not necessary. In addition, due to the large number of available I/O pins on the FPGA, there are sufficient dedicated I/O pins available so that these shared pins do not need to be reused in our design.

=== FPGA/EEPROM Pull-up Resistors ===

=== FPGA/EEPROM Pull-up Resistors ===