Changes

== Our packets ==

== Packets from the PC to the FPGA ==

We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle.  Each packet's data section will begin with a single-byte code to identify the packet type.  As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.

We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle.  Each packet's data section will begin with a single-byte code to identify the packet type.  As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.

=== The reset cycle ===

=== The reset cycle - "R" packets ===

[[Image:OperationCourse.png|thumb|255px|Operation course between the digital board and the controller PC]]

[[Image:OperationCourse.png|thumb|255px|Operation course between the digital board and the controller PC]]

Additionally, the reset cycle gives the tagger boards and PC a chance to build the proper address maps. The boards acquire the MAC address of the PC and the PC builds a MAC-Location table, where the "Location" is a hard-coded 8-bit slot identifier hard-coded into the bus-board. This organization step is necessary for the PC to be able to pinpoint SiPM channel groups.

Additionally, the reset cycle gives the tagger boards and PC a chance to build the proper address maps. The boards acquire the MAC address of the PC and the PC builds a MAC-Location table, where the "Location" is a hard-coded 8-bit slot identifier hard-coded into the bus-board. This organization step is necessary for the PC to be able to pinpoint SiPM channel groups.

 

The "R group" of packets sent from the PC to the card to initiate a reset process in various forms.  Two possible reset packets (corresponding to two degrees of reset) are possible

==== "R" packets: reset ====

 

This group of packets sent from the PC to the card to initiate a reset process in various forms.  Two possible reset packets (corresponding to two degrees of reset) are possible

* Full or "Hard" reset: This resets all chips on the board. This will contain no data as no further instructions can be remembered after a board reset.

* Full or "Hard" reset: This resets all chips on the board. This will contain no data as no further instructions can be remembered after a board reset.

* Selective or "Soft" reset: This will have flags to reset the Ethernet chip, the ADC/Temperature sensor group (SPI bus), and the DAC.   

* Selective or "Soft" reset: This will have flags to reset the Ethernet chip, the ADC/Temperature sensor group (SPI bus), and the DAC.   

===== R-packet - hard reset =====

===== R-packet - hard reset =====

The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPAG_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC) loads its own MAC address and transmits an [[#"S" packet: status report]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).

The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPAG_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC) loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).

 

  For a full-reset-only design, all remaining bytes in the packet will be padding that the FPGA can ignore.  For a selective-reset design, the second data byte will contain the four flags, and all bytes after that will be padding.  A selective-reset design allows a form of "Are you awake" query to the board: Send a reset packet with all reset flags turned off; the system will not reset any devices but will still respond with an "I" packet.  This may be an unnecessary feature, as the query cycle already acts as a more complex "Are you awake" query.

===== R'-packet - soft reset =====

==== "I" packet: initialization complete ====

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPAG_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partnet) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

=== The query cycle ===

=== The query cycle - "Q" packet ===

The query cycle is a conversation regarding the status of the digital board.  It polls the sensor devices and reports back their most recent data.   

The query cycle is a conversation regarding the status of the digital board.  It polls the sensor devices and reports back their most recent data.   

==== "Q" packet: query ====

The Q-packet is sent from the PC to the FPGA to request a status report from its sensor chips. Again, there is no relevant data aside from the packet type. There is no data attached to a query packet: the FPGA triggers the [[FPGA_Querier|query module]] upon recognizing a Q-type packet, which is identifiedan ASCII '''Q''': 0x51, 0101 0001 in the packet type field (2nd byte of packet payload)

 

This is the packet sent from the PC to the FPGA to request a status report.  This could be made selective (status of ADC only, status of temperature sensor only, or full status report). However, as the size of an Ethernet packet is so large compared to the amount of data being requested, all data will be sent and the PC can use the data as it desires. Thus there is no data attached to a query packet.  The first byte is an ASCII '''Q''': 0x51, 0101 0001.

 

==== "S" packet: status report ====

=== The programming cycle ===

=== The programming cycle - "P" Packet===

The programming cycle is a conversation intended to set the values of the DAC channels.  It sends programming data to the board and receives confirmation of the programming.

The programming cycle is a conversation intended to set the values of the DAC channels.  It sends programming data to the board and receives confirmation of the programming.

This is the packet sent from the PC to the FPGA to set new values to the DAC channels.  The first byte of the packet will be an ASCII '''P''': 0x50, 0101 0000.  The next four bytes (if all 32 channels are used; 3 if 24 channels, 2 bytes if 16 channels) together form a programming mask.  Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 31 (or 23 or 15) and the LSB of the fourth (or third or second) byte will be channel 0.  Thus, if all 32 channels are to be used, but only channels 14 through 26 are to be programmed, the packet would contain:

This is the packet sent from the PC to the FPGA to set new values to the DAC channels.  The first byte of the packet will be an ASCII '''P''': 0x50, 0101 0000.  The next four bytes (if all 32 channels are used; 3 if 24 channels, 2 bytes if 16 channels) together form a programming mask.  Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 31 (or 23 or 15) and the LSB of the fourth (or third or second) byte will be channel 0.  Thus, if all 32 channels are to be used, but only channels 14 through 26 are to be programmed, the packet would contain:

| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0

| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0

|}

|}

Following this are 64 (or 48 or 32) bytes of programming data.  The first two bytes are for channel 31 (or 23 or 15) and the last two bytes are for channel 0. Each channel has 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  The total size of the data in a programming packet is:

Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  The total size of the data in a programming packet is:

{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"

 

! Number of channels

 

 

|-

=== "S" packet: status report ===

 

This is the packet sent from the FPGA to the PC to report on the current status of the board.  The first two bytes of the packet will be the usual Location-stamp byte and the packet identifier: an ASCII '''S''': 0x53, 0101 0011.  After that will come the status data.

* The first two bytes of data will be the temperature. The temperature sensor returns 10 bits of data.  The first byte will contain six leading zeros, then the two MSB of data.  The second byte will contain the 8 LSB of data.

* The next 16 bytes of data will be the ADC channels.  The ADC returns 8 channels of 12 bits each.  The first byte for each channel will have four leading zeros, then the 4 MSB of the data.  The second byte for each channel will contain the 8 LSB of the data.  The channels will be reported from channel zero to channel seven.

| 16 ||      || 35^*

This totals 20 bytes: one for Location, one for Packet Type, two of temperature, sixteen of voltages.

 

Since the minimum number of data bytes in a packet is 46, the packet may need to be padded if only 16 channels are to be used.  Alternately the mask can be eliminated, forcing all channels of the DAC to be reprogrammed every programming cycle; however, having a mask allows a query of all DAC channels: set the mask to all zeros to reprogram nothing and the response will report back channel values according to the FPGA.

==== "D" packet: DAC setup complete ====

=== "D" packet: DAC setup complete ===

This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100.  The next 64 (or 48 or 32) bytes are the values of each DAC channel.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte, channel 31 (or 23 or 15) first, channel 0 last. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. This will require that the FPGA (or the RAM in the Ethernet chip) store the values of the DAC channels, as the DAC has no interface to report back the value of a given channel. The size of this packet will be 4 (or 3 or 2) bytes less than for the corresponding programming packet, to account for the programming mask.

This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications.  The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100.  The next 64 bytes are the values of the DAC channels.  As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte. The channel values are listed from 0 to 31. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC.  All channels are reported back, not just those that were reprogrammed during this conversation. Note that the DAC chip has no interface for querying the state of particular channels. The values reported are the nominal programmed values simply confirming that the correct values were received. If there remain free ADC channels, they can perhaps be wired to sample some DAC lines in order to have some real confirmation.