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→Programming Details of Rest_hard
== Programming Details of Rest_hard ==
== Programming Details ==
The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1.
The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1.
* ''Clk'': [in] clock
* ''Clk'': [in] clock
* ''Rst: [in] asynchronous reset
[[FPGA_Registers#State_Register|State Register]] Control Lines
* ''state_En'': [out] state register enable (write) signal
* ''state_D'': [out] (3-bit) state register input
* ''state_Q'': [in] (3-bit) state register output
* ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot
[[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines
* ''MACregs_A'': [out] byte address (4-bit)
* ''MACregs_Q'': [in] 8-bit value
[[FPGA_Registers#Temperature Register|Temperature]], [[FPGA_Registers#ADC Register|ADC]] and [[FPGA_Registers#DAC Register|DAC]] register control lines
* ''Rst: [in] asynchronous reset
* ''TempReg_Q'': [in] 16-bit (front-padded 10-bit) Temperature register value
* ''ADCReg_Addr'': [out] 3-bit ADC register address
* ''ADCReg_Q'': [in] 16-bit (front-padded 12-bit) ADC register value
* ''DACReg_Addr'': [out] 5-bit DAC register address bus
* ''DACReg_Q : [in] 16-bit (front-padded 14-bit) DAC register value
[[FPGA_Transceiver|Transceiver]] Control Lines
* ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte
* ''TxRx_RiW'': [out] active-high read, active-low write flag
* ''TxRx_Aout'': [out] EC control register address (8-bit)
* ''TxRx_Dout'': [out] EC control register write value
* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]
== (111) Transmit "D" ==
== (111) Transmit "D" ==