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Line 1: − == (101) Transmit "S" ==+ − This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.+ − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset − * ''State'': 3-bit state value − internal signals+ − * ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'') − * ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle − blocks+ − * '''Temp Loader'''+ − ** This block reads the temperature value from the internal registers and loads it to the transmit buffer.+ − ** inputs+ − *** ''Clk'': clock+ − *** ''/Rst'': asynchronous, active-low reset+ − *** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101+ − *** ''D_in'': 16-bit data bus from internal registers+ − *** ''TxRx_Done'': ''Done'' signal from transceiver+ − ** ouputs+ − *** ''TxRx_Go'': ''Go'' signal on transceiver+ − *** ''TxRx_R/W'': ''R/W'' signal on transceiver+ − *** ''TxRx_A'': ''A_in'' bus on transceiver − *** ''TxRx_D'': ''D_in'' bus on transceiver − *** ''Done'': pulse to signal completion − * '''ADC Loader''' − ** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader − *** ''D_in'': 16-bit data bus from internal registers − *** ''TxRx_Done'': ''Done'' signal from transceiver − ** ouputs − *** ''Sel'': 3-bit select bus for internal registers − *** ''TxRx_Go'': ''Go'' signal on transceiver − *** ''TxRx_R/W'': ''R/W'' signal on transceiver − *** ''TxRx_A'': ''A_in'' bus on transceiver − *** ''TxRx_D'': ''D_in'' bus on transceiver − *** ''Done'': pulse to signal completion − * '''Padder''' − ** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader − *** ''TxRx_Done'': ''Done'' signal from transceiver − ** outputs − *** ''TxRx_Go'': ''Go'' signal on transceiver − *** ''TxRx_R/W'': ''R/W'' signal on transceiver − *** ''TxRx_A'': ''A_in'' bus on transceiver − *** ''TxRx_D'': ''D_in'' bus on transceiver − *** ''Done'': pulse to signal completion − * '''Sender''' − ** This block tells the CP2200/1 to send the completed packet. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder − *** ''TxRx_Done'': ''Done'' signal from transceiver − ** outputs − *** ''TxRx_Go'': ''Go'' signal on transceiver − *** ''TxRx_R/W'': ''R/W'' signal on transceiver − *** ''TxRx_A'': ''A_in'' bus on transceiver − *** ''TxRx_D'': ''D_in'' bus on transceiver − *** ''Done'': pulse to signal completion
no edit summary
= (1X1) Transmitter =
The Transmitter is responsible for compiling report packets for sending to the PC. As discussed [[Ethernet packets#"S" packet: status report|elsewhere]], the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the [[FPGA_Idler|Idler]] to await the next request from the PC.
== Programming Details of Rest_hard ==
The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1.
The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the ''RAwrToAddr'' (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored.
=== Ports ===
* ''Clk'': [in] clock
Reset Signals
* ''Rst: [in] asynchronous reset