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Line 62: + − + − ; (000) Reset Cycle+ − : The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.+ − ; <s>(001) Transmit "I"</s> − : <s>This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.</s> "S"-Packet (from state 101) would do just as well, returning zeroed registers, location address etc for computer's address LUT. − ; (010) Idle − : This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011. − ; (011) Read Packet − : This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010. − ; (100) Poll Status − − ; (101) Transmit "S" − : This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet. − ; (110) Program DAC − : This state programs the DAC with new values according to the mask and data in the "P" packet. − ; (111) Transmit "D" − : This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet. − − == State interconnect == − − These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. This implementation calls for a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block. With several modules writing to the register, usual precautions must be taken to avoid more than one drivers forcing a line simultaneously. All modules must be designed to go to high impedance on their output lines when they are not active. − − == State variable == − − Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful. − − ** S<sub>2</sub> = 0: "Core cycle" that executes regularly and forms the spine of the state diagram. − *** S<sub>2:1</sub> = 00: "Initialization cycle" that prepares the state diagram for normal functioning. − *** S<sub>2:1</sub> = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches. − ** S<sub>2</sub> = 1: "Branch cycles" that execute selectively based on received packets. − *** S<sub>2:1</sub> = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]]. − − * S<sub>0</sub>: − ** S<sub>0</sub> = 0: "Setup state" to prepare internal workings for a communication. − ** S<sub>0</sub> = 1: "Transfer state" to communicate with the external PC. − − − = Controller = − − == Foreword on Timing == − − With a controller this complex, the timing of signals must be inspected even more scrupulously than usual. In particular, simultaneous transitions of data and "Done" lines must be avoided. When possible, a one-cycle-delayed "Done" signal is used to ensure that the data lines have been stabilized. (All delays are implemented via the <tt>c_delay</tt> module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle). When this is inconvenient (e.g. when writing to registers) the target component must not be enabled on rising edges on "Go" or the clock. The registers, for instance, have been designed to read values on the ''falling edge'' of the clock - middle of the "Go" pulse, safely after the data line transitions. − − − − − − − − − (Packet type inspection) − − (status query module)]] − − − − − [[FPGA_Registers|Registers]] − [[FPGA_Reusables|Miscellaneous Reusable Components]]
Programming the Ethernet controller (view source)
Revision as of 18:15, 19 May 2008
, 18:15, 19 May 2008no edit summary
In our design, the modules involved with packet handling and interfacing with sensor chip controllers are organized by ''state''. A state register specifies the current stage of the process and only the corresponding module is allowed to act during that stage. Aside from defining a process sequence, the state serves as a complex "enable" signal for the modules, ensuring that only one module is driving the communication bus used to query the EC.
In our design, the modules involved with packet handling and interfacing with sensor chip controllers are organized by ''state''. A state register specifies the current stage of the process and only the corresponding module is allowed to act during that stage. Aside from defining a process sequence, the state serves as a complex "enable" signal for the modules, ensuring that only one module is driving the communication bus used to query the EC.
= Controller =
== Foreword on Timing ==
= The eight states =
With a controller this complex, the timing of signals must be inspected even more scrupulously than usual. In particular, simultaneous transitions of data and "Done" lines must be avoided. This is solved by either
# a one-cycle-delayed "Done" signal to ensure that the data lines have been stabilized. (All delays are implemented via the <tt>c_delay</tt> module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle).
# coding the target component to read the data lines on the ''falling edge'' of the clock during the a "Go" signal.
The latter method turned out to be the dominant one in this design.
== The eight states ==
=== State-Module organization ===
The core of the the FPGA is divided roughly into eight modules enabled by by the 3-bit state value. Below is an index of the states and their corresponding modules. In this discussion of states, 'X' is a binary wild card the values are immediately explained.
The core of the the FPGA is divided roughly into eight modules enabled by by the 3-bit state value. Below is an index of the states and their corresponding modules. In this discussion of states, 'X' is a binary wild card the values are immediately explained.
|}
|}
= Interface =
=== State interconnect ===
As described above, these states form the outline of the functional block diagram. This implementation calls for a central ''state register''. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block. With several modules writing to the register, usual precautions must be taken to avoid more than one drivers forcing a line simultaneously. All modules must be designed to go to high impedance on their output lines when they are not active.
== Interface ==
[[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]]
[[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]]
== Miscellaneous non-state-based components ===
Please refer to the individual design detail pages for:
* [[FPGA_Registers|Registers]]
* [[FPGA_Reusables|Miscellaneous Reusable Components]]
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
* S<sub>2:1</sub>:
*** S<sub>2:1</sub> = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
= Emulator =
= Emulator =