Changes

=== Random Access Write (<tt>RAwrToAddr</tt>) ===

=== Random Access Write (<tt>RAwrToAddr</tt>) ===

Writing directly to Ethernet Controller RAM requires more work in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, being out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions.

Writing directly to Ethernet Controller RAM (not to be confused with the control registers) in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time to appropriate control registers and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, as it is out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions.

 

 

 

Because the data values exchanged between the board and the PC range from 10 to 14 bit depth, zero padded 16-bit words will be used. So, to load this 2-byte word into the transfer buffer requires two random access writes.  This module packages this functionality by including two calls to <tt>RAwrToAddr</tt> with address increments and input data latching taken into account.

=== Miscellaneous Components ===

=== Miscellaneous Components ===