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==== transceiver ====
 
==== transceiver ====
   −
This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA.  It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.  The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
+
This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA.  It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.  The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
    
inputs
 
inputs
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inouts
 
inouts
 
* ''AD'': 8-bit address and data bus
 
* ''AD'': 8-bit address and data bus
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==== State Register ====
 
==== State Register ====
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outputs
 
outputs
 
* ''Q'': three-bit data-out bus
 
* ''Q'': three-bit data-out bus
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==== temperature register ====
 
==== temperature register ====
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outputs
 
outputs
 
* ''Q'': ten-bit data-out bus
 
* ''Q'': ten-bit data-out bus
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==== ADC registers ====
 
==== ADC registers ====
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outputs
 
outputs
 
* ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
 
* ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
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==== DAC registers ====
 
==== DAC registers ====
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outputs
 
outputs
 
* ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus
 
* ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus
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==== Reusable Components ====
 
==== Reusable Components ====
   −
===== Components Interface with Transceiver =====
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Several components were found useful as reusable units rather than unique modules.
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===== Byte Fetcher (<tt>getByte</tt>) =====
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Fetches a byte of data from the Ethernet Controller control and data registers. This unit helps abstract and package the communication steps with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". Aside from packaging, the component ensures proper timing among the sent signals. The actual request is performed via the <tt>reqFromAddr</tt> unit described below.
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===== Auto-reader (<tt>AutoRd</tt>) =====
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Performs the same function as the Byte Fetcher (described above) but is hard-wired to address the RXAUTORD (0x01). This is convenient because the Ethernet Controller's AutoRead interface will be used extensively to parse through packets. <tt>AutoRd</tt> is in fact a wrapper around <tt>GetByte</tt> passing through all signals accept the fixed address input.
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===== Read Request (<tt>reqFromAddr</tt>) =====
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Sends request for reading (R/W pin high) to transceiver at the specified address. "Go" pulse is appropriately delayed to ensure that parameter signals sent to transceiver have gone through their transitions. This unit is not intended for direct use, but rather to be the core of the fetcher components described above.
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===== Write Request (<tt>reqFromAddr</tt>) =====
    +
Sends a write request (R/W pin low) to transceiver at the specified address with the specified byte of data. The primary reason of this instruction "packaging" is to obscure the complexity of appropriate delays to ensure proper signal latching.
    
===== Miscellaneous Components =====
 
===== Miscellaneous Components =====
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