Changes

=== Non-State Components ===

=== Non-State Components ===

* '''transceiver'''

==== transceiver ====

** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA.  It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.  The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.

 

** inputs

This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA.  It takes information on the next transfer to carry out and returns information on the last transfer completed.  It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer.  This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.  The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.

*** ''CLK'': clock

 

*** ''/Rst'': asynchronous, active-low reset

inputs

*** ''Go'': pulse to begin a transmission

* ''CLK'': clock

*** ''R/W_in'': read/write toggle: active-high read, active-low write

* ''/Rst'': asynchronous, active-low reset

*** ''A_in'': 8-bit bus for address to read to/write from

* ''Go'': pulse to begin a transmission

*** ''D_in'': 8-bit bus for data to write; ignored during a read

* ''R/W_in'': read/write toggle: active-high read, active-low write

** outputs to internals

* ''A_in'': 8-bit bus for address to read to/write from

*** ''Done'': pulse to signal completion of a transmission

* ''D_in'': 8-bit bus for data to write; ignored during a read

*** ''R/W_out'': read/write flag: active-high read, active-low write

 

*** ''A_out'': 8-bit bus for address of last read/write

outputs to internals

*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write

* ''Done'': pulse to signal completion of a transmission

** outputs to CP2200/1

* ''R/W_out'': read/write flag: active-high read, active-low write

*** ''/CS'': active-low chip select

* ''A_out'': 8-bit bus for address of last read/write

*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel

* ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write

*** ''MuxEn'': Multiplexed flag; not used for CP2201

 

*** ''ALE'': ALE strobe

* outputs to CP2200/1

*** ''/Wr'': Active-low write flag

* ''/CS'': active-low chip select

*** ''/Rd'': Active-low read flag

* ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel

** inouts

* ''MuxEn'': Multiplexed flag; not used for CP2201

*** ''AD'': 8-bit address and data bus

* ''ALE'': ALE strobe

* ''/Wr'': Active-low write flag

** A three-bit register to store the current state.

* ''/Rd'': Active-low read flag

** inputs

 

*** ''Clk'': clock

inouts

*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

* ''AD'': 8-bit address and data bus

*** ''En'': write enable

 

*** ''D'': three-bit data-in bus

** outputs

A three-bit register to store the current state.

*** ''Q'': three-bit data-out bus

inputs

* '''temperature register'''

* ''Clk'': clock

** A 16-bit register to store the most recent temperature data.

* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

** inputs

* ''En'': write enable

*** ''Clk'': clock

* ''D'': three-bit data-in bus

*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

 

*** ''En'': write enable

outputs

*** ''D'': ten-bit data-in bus

* ''Q'': three-bit data-out bus

** outputs

 

*** ''Q'': ten-bit data-out bus

==== temperature register ====

* '''ADC registers'''

A 16-bit register to store the most recent temperature data.

** A set of eight 16-bit registers to store the most recent ADC data.  Also includes a demultiplexer to select which register to write to.

inputs

** inputs

* ''Clk'': clock

*** ''Clk'': clock

* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

* ''En'': write enable

*** ''En'': write enable

* ''D'': ten-bit data-in bus

*** ''S'': 3-bit select bus

 

*** ''D'': 12-bit data-in bus

outputs

** outputs

* ''Q'': ten-bit data-out bus

*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus

 

* '''DAC registers'''

==== ADC registers ====

** A set of 32/24/16 16-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to.

A set of eight 16-bit registers to store the most recent ADC data.  Also includes a demultiplexer to select which register to write to.

** inputs

inputs

*** ''Clk'': clock

* ''Clk'': clock

*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

*** ''En'': write enable

* ''En'': write enable

*** ''S'': 5/5/4-bit select bus

* ''S'': 3-bit select bus

*** ''D'': 14-bit data-in bus

* ''D'': 12-bit data-in bus

** outputs

 

*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

outputs

* ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus

 

==== DAC registers ====

A set of 32/24/16 16-bit registers to store the most recent DAC data.  Also includes a demultiplexer to select which register to write to.

inputs

* ''Clk'': clock

* ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)

* ''En'': write enable

* ''S'': 5/5/4-bit select bus

* ''D'': 14-bit data-in bus

 

outputs

* ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

 

 

 

 

=== (000) Reset Cycle ===

=== (000) Reset Cycle ===