461
edits
Changes
Jump to navigation
Jump to search
Line 210:
Line 210: + + Line 243:
Line 245: − + − *** ''D_En'': high when DAC is to be reset+ − *** ''D_Done'': high when DAC is done resetting+ − *** ''A_En'': high when ADC is to be reset − − *** ''E_En'': high when Ethernet controller is to be reset − − + − +
Programming the Ethernet controller (view source)
Revision as of 16:24, 19 July 2007
, 16:24, 19 July 2007→(100) Poll Status
This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.
This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.
Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.
inputs
inputs
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
** inputs
*** ''Clk'': clock
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
*** ''T_Done'': high when temperature sensor is done polling
*** ''A_Done'': high when ADC is done resetting
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
*** ''Flag'' <= ''A_done'' and ''T_Done''
** outputs
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high
=== (101) Transmit "S" ===
=== (101) Transmit "S" ===