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Programming the Ethernet controller (view source)
Revision as of 16:21, 19 July 2007
, 16:21, 19 July 2007→(100) Poll Status
This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.
This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 12-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''T_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high
=== (101) Transmit "S" ===
=== (101) Transmit "S" ===