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=== The Ethernet controller ===
=== The Ethernet controller ===
The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization"). The main points of the process will be covered here.
* The first step is to wait for the reset pin to rise. No flag will be raised upon the completion of this step other than the reset pin (which is an input to the CP2200/1) being high.
* The second step is to wait for Oscillator Initialization to complete. Completion of this will be signaled by an interrupt request signal.
* The third step is to wait for Self Initialization to complete. Completion of this will also be signaled by an interrupt request signal.
* At this point all interrupts will be enabled. Any interrupts which the FPGA will not handle should be disabled now.
* The physical layer must be initialized, which is itself a multi-step process.
** See section 15.7 "Initializing the Physical Layer"
** If auto-negotiation is to be used see section 15.2 "Auto-Negotiation Synchronization."
* Enable the Link, Act, or Activity/Link LED(s).
* The MAC must now be initialized, another multi-step subprocess.
** See section 14.1 "Initializing the MAC."
* The receive filter must now be configured.
** See section 12.4 "Initializing the Receive Buffer, Filter and Hash Table."
* The CP2200/1 is now ready for regular operation.