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On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle|reset the system on a command from the PC]].
On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle|reset the system on a command from the PC]].
=== The DAC ===
The AD5535 DAC has an active-low reset pin. Pulling that pin low will reset the DAC, zeroing all channels.
=== The temperature sensor ===
The AD7314 temperature sensor does not have a reset function. It self-initializes on powering up.
=== The ADC ===
The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up. The reset procedure is to hold the ''D<sub>in</sub>'' line high while performing two dummy conversions. During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA. It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.
=== The Ethernet controller ===