461
edits
Changes
Jump to navigation
Jump to search
Line 179:
Line 179: + + + + + + + + + + + + + + + + + + + + + + +
no edit summary
== The ADC ==
== The ADC ==
The VHDL files are currently being developed.
=== Interface (A) ===
=== Interface (A) ===
The AD7928 ADC has several features that we do not need: the shadow/sequencer and the multiple power modes. They could be useful for more advanced or efficient functioning of the system, but are not needed. Thus we will simplify the interface by turning these features off and running the ADC is the most basic mode.
The ADC has a four-wire interface that is compatible with the SPI bus protocol. The four lines are:
* ''/CS'': Active-low chip select. This line is high when the ADC is idle and goes low for 16 cycles during a conversation. As this is active-low and the only other chip on the bus (the temperature sensor) has an active-high chip select line, it is possible to use a single chip select. That would cause one or the other chip to always be running, which would be more information than we need or than we can send across Ethernet, but it is a possible design decision.
* ''SCLK'': A serial clock.
* ''D_out'': Serial data out line, for communications from the ADC to the FPGA. This line idles in high-Z.
* ''D_in'': Serial data in line, for communications from the FPGA to the ADC.
On startup the ADC requires two "dummy" conversation that write all ones to the ADC and read garbage data from the ADC.
A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC. The 12-bit control register has the following format:
{| align="center" cellpadding="1" border="1" cellspacing="1"
|
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
| 11 || 10 || 09 || 08 || 07 || 06 || 05 || 04 || 03 || 02 || 01 || 00
|-
| Write || Seq || DC || Addr<sub>2</sub> || Addr<sub>1</sub> || Addr<sub>0</sub> || Pow<sub>1</sub> || Pow<sub>0</sub> || Shadow || DC || Range || Coding
|}
|}
=== Emulator (A) ===
=== Emulator (A) ===