Changes

[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]

[[Image:ISE - RTL.PNG|thumb|left|125px|The Register Transfer Level Schematic.]]

Once you've synthesized your design, double click on "View RTL Schematic".  RTL stands for Register Transfer Level.  This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together.  As discussed in previous sections, a thick wire is a bus.  By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus.  Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows.  Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows.  Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other.  You can also double click "View Technology Schematic."  This is similar to the RTL schematic, however there is no blocking of components together functionally, nor will multiple lines be combined into buses.  It can be a rather large, intimidating, and confusing view so it is not often used, as RTL gives the same information in a much more comprehensible fashion.

Once you've synthesized your design, double click on "View RTL Schematic".  RTL stands for Register Transfer Level.  This gives you what is effectively a block diagram of your circuit, with all the gates and parts in place and wired together.  As discussed in previous sections, a thick wire is a bus.  By extension, a part drawn with thick lines has bus I/O but performs the same function for all lines of the bus.  Inputs are shown on the left as arrows pointing to the right with lines and buses coming off the points of the arrows.  Outputs are shown on the right as arrows pointing to the right with lines and buses entering the flat ends of the arrows.  Branches of the wires are shown as dots at the intersection points; intersections without dots are separate wires that happen to cross without connecting to each other.  To enter a block, simply double click on it.  To exit a block and go back to the next higher schematic, you can right click and select "Pop to the Calling Schematic."

 

You can also double click "View Technology Schematic."  This is similar to the RTL schematic, however there is no blocking of components together functionally, nor will multiple lines be combined into buses.  It can be a rather large, intimidating, and confusing view so it is not often used, as RTL gives the same information in a much more comprehensible fashion.

== Simulation ==

== Simulation ==

Once you have defined your input waveforms (don't bother trying to set your output waveforms; those get defined by the simulator), you are now ready to simulate.  Go to the Processes box and double click "Simulate Behavioral Model" (under "Xilinx ISE Simulator").  ISE will think for a bit then open a new window like the one shown to the right.  This shows the input and output signal waveforms.  You can see the internal bus ''count'' (highlighted) expanded to show both the bus notation mentioned above (values in hex) and the individual line waveforms.  You'll have to study these waveforms closely to debug many of your designs.  Timing hazards may appear here (a signal fires a clock cycle too early or too late and ruins the synchronization of the entire device, etc.).  If you look over this design and decide you are happy with the output, then you have successfully designed and done basic testing in VHDL.

Once you have defined your input waveforms (don't bother trying to set your output waveforms; those get defined by the simulator), you are now ready to simulate.  Go to the Processes box and double click "Simulate Behavioral Model" (under "Xilinx ISE Simulator").  ISE will think for a bit then open a new window like the one shown to the right.  This shows the input and output signal waveforms.  You can see the internal bus ''count'' (highlighted) expanded to show both the bus notation mentioned above (values in hex) and the individual line waveforms.  You'll have to study these waveforms closely to debug many of your designs.  Timing hazards may appear here (a signal fires a clock cycle too early or too late and ruins the synchronization of the entire device, etc.).  If you look over this design and decide you are happy with the output, then you have successfully designed and done basic testing in VHDL.