Changes

To set the values, simply click on the waveforms wherever you want the value to be toggled.  If you wish to use one of the 7 non-binary logic levels ([[VHDL_tutorial#VHDL_Resolution_Table|shown here]]) or to set a pattern for ISE to fill in for you, right click on the waveform where you wish to start the pattern or non-binary logic level and select "Set Value."  Beware of having too many transitions, as it is possible to crash the program that way.

To set the values, simply click on the waveforms wherever you want the value to be toggled.  If you wish to use one of the 7 non-binary logic levels ([[VHDL_tutorial#VHDL_Resolution_Table|shown here]]) or to set a pattern for ISE to fill in for you, right click on the waveform where you wish to start the pattern or non-binary logic level and select "Set Value."  Beware of having too many transitions, as it is possible to crash the program that way.

Once you have defined your input waveforms (don't bother trying to set your output waveforms; those get defined by the simulator), you are now ready to simulate.  Go to the Processes box and double click "Simulate Behavioral Model" (under "Xilinx ISE Simulator").  ISE will think for a bit then open a new window like the one shown to the right.

 

Once you have defined your input waveforms (don't bother trying to set your output waveforms; those get defined by the simulator), you are now ready to simulate.  Go to the Processes box and double click "Simulate Behavioral Model" (under "Xilinx ISE Simulator").  ISE will think for a bit then open a new window like the one shown to the right.  This shows the input and output signal waveforms.  You can see the internal bus ''count'' (highlighted) expanded to show both the bus notation mentioned above (values in hex) and the individual line waveforms.  You'll have to study these waveforms closely to debug many of your designs.  Timing hazards may appear here (a signal fires a clock cycle too early or too late and ruins the synchronization of the entire device, etc.).  If you look over this design and decide you are happy with the output, then you have successfully designed and done basic testing in VHDL.