Changes

You give the component an identifier.  Customarily engineers use the U numbering system (U followed by a number, starting at 1 and going until you run out of components).  But you can give the component map any identifier you see fit.  Then you give the component name, the words "port map", then a list of signals or pins.  The signal listed first in the port map will be connected to the pin listed first in the component declaration, and so on down the line.  And that's all you have to do to include components in your design.  The synthesizer will retrieve the appropriate code and make the connections for you.

You give the component an identifier.  Customarily engineers use the U numbering system (U followed by a number, starting at 1 and going until you run out of components).  But you can give the component map any identifier you see fit.  Then you give the component name, the words "port map", then a list of signals or pins.  The signal listed first in the port map will be connected to the pin listed first in the component declaration, and so on down the line.  And that's all you have to do to include components in your design.  The synthesizer will retrieve the appropriate code and make the connections for you.

== VHDL Resolution Table ==

VHDL STD_LOGIC and STD_LOGIC_VECTOR both operate on 9-value logic defined by IEEE.  The nine states are:

 

{| style="text-align:center"

{| style="text-align:center"

|+VHDL Resolution Table

|+ '''VHDL Resolution Table'''

|-

|-

!  !! U !! X !! 0 !! 1 !! Z !! W !! L !! H !! –

!  !! U !! X !! 0 !! 1 !! Z !! W !! L !! H !! –

| U || X || X || X || X || X || X || X || X

| U || X || X || X || X || X || X || X || X

|}

|}