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no edit summary
<pre>
<pre>
architecture DAC_emul_arch of DAC_emulator is
architecture arch_name of component_name is
signal line_sig : STD_LOGIC; -- an internal signal line
signal line_sig : STD_LOGIC; -- an internal signal line
signal bus_sig : STD_LOGIC_VECTOR (4 downto 2); -- a 3-bit internal signal bus
signal bus_sig : STD_LOGIC_VECTOR (4 downto 2); -- a 3-bit internal signal bus
-- code goes here --
-- code goes here --
--------------------
--------------------
end DAC_emul_arch;
end arch_name;
</pre>
</pre>
A software engineer looks at this and thinks it's quite simple. First to execute is ''statement_1'', followed by ''statement_2''. Then the loop is executed: the first iteration, followed by the second, all the way down to the fifth being the last part of the loop. Finally ''statement_4'' is executed and the program terminates. In software you'd be correct.
A software engineer looks at this and thinks it's quite simple. First to execute is ''statement_1'', followed by ''statement_2''. Then the loop is executed: the first iteration, followed by the second, all the way down to the fifth being the last part of the loop. Finally ''statement_4'' is executed and the program terminates. In software you'd be correct.
Now let's consider how this would run in VHDL. Very simply: everything happens ''at once''. If ''statement_1'' modifies signal x from 7 to 19 and ''statement_2'' reads statement x, what value will ''statement_2'' read? '''7'''. Not 19, because the two statements are simultaneous. The same is true of the loop. Iteration 1 comes no sooner than (and no later than) iteration 5. So you need to keep that in mind: everything is simultaneous, regardless of where and how you type it into the code. Forget that and you may never figure out why your circuit is trying to eat itself.
Now let's consider how this would run in VHDL. Very simply: everything happens ''at once''. If ''statement_1'' modifies signal X from 7 to 19 and ''statement_2'' reads signal X, what value will ''statement_2'' read? '''7'''. Not 19, because the two statements are simultaneous. The same is true of the loop. Iteration 1 comes no sooner than (and no later than) iteration 5. So you need to keep that in mind: everything is simultaneous, regardless of where and how you type it into the code. Forget that and you may never figure out why your circuit is trying to eat itself.
=== The basics: combinational logic ===
=== The basics: combinational logic ===
Let's start simple. Combinational logic just takes the lines and mixes them together to create a new set of lines. You have the whole range of usual logical operators: AND, OR, NOR, NAND, XOR, XNOR, NOT, and whatever else you can dream up and assemble. To see an example of combinational logic at work, take a look at the code for the 5-to-32 demultiplexer included in the emulator.
<pre>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DAC_demux is
Port ( S : in STD_LOGIC_VECTOR (4 downto 0); -- 5-bit select
D : in STD_LOGIC; -- data to demux
Q : out STD_LOGIC_VECTOR (31 downto 0)); -- 32 output lines
end DAC_demux;
architecture DAC_demux_arch of DAC_demux is
begin
-- combinational logic to implement demux
Q(0) <= D and not (S(4)) and not(S(3)) and not(S(2)) and not(S(1)) and not(S(0));
Q(1) <= D and not (S(4)) and not(S(3)) and not(S(2)) and not(S(1)) and S(0);
Q(2) <= D and not (S(4)) and not(S(3)) and not(S(2)) and S(1) and not(S(0));
Q(3) <= D and not (S(4)) and not(S(3)) and not(S(2)) and S(1) and S(0);
Q(4) <= D and not (S(4)) and not(S(3)) and S(2) and not(S(1)) and not(S(0));
Q(5) <= D and not (S(4)) and not(S(3)) and S(2) and not(S(1)) and S(0);
Q(6) <= D and not (S(4)) and not(S(3)) and S(2) and S(1) and not(S(0));
Q(7) <= D and not (S(4)) and not(S(3)) and S(2) and S(1) and S(0);
Q(8) <= D and not (S(4)) and S(3) and not(S(2)) and not(S(1)) and not(S(0));
Q(9) <= D and not (S(4)) and S(3) and not(S(2)) and not(S(1)) and S(0);
Q(10) <= D and not (S(4)) and S(3) and not(S(2)) and S(1) and not(S(0));
Q(11) <= D and not (S(4)) and S(3) and not(S(2)) and S(1) and S(0);
Q(12) <= D and not (S(4)) and S(3) and S(2) and not(S(1)) and not(S(0));
Q(13) <= D and not (S(4)) and S(3) and S(2) and not(S(1)) and S(0);
Q(14) <= D and not (S(4)) and S(3) and S(2) and S(1) and not(S(0));
Q(15) <= D and not (S(4)) and S(3) and S(2) and S(1) and S(0);
Q(16) <= D and S(4) and not(S(3)) and not(S(2)) and not(S(1)) and not(S(0));
Q(17) <= D and S(4) and not(S(3)) and not(S(2)) and not(S(1)) and S(0);
Q(18) <= D and S(4) and not(S(3)) and not(S(2)) and S(1) and not(S(0));
Q(19) <= D and S(4) and not(S(3)) and not(S(2)) and S(1) and S(0);
Q(20) <= D and S(4) and not(S(3)) and S(2) and not(S(1)) and not(S(0));
Q(21) <= D and S(4) and not(S(3)) and S(2) and not(S(1)) and S(0);
Q(22) <= D and S(4) and not(S(3)) and S(2) and S(1) and not(S(0));
Q(23) <= D and S(4) and not(S(3)) and S(2) and S(1) and S(0);
Q(24) <= D and S(4) and S(3) and not(S(2)) and not(S(1)) and not(S(0));
Q(25) <= D and S(4) and S(3) and not(S(2)) and not(S(1)) and S(0);
Q(26) <= D and S(4) and S(3) and not(S(2)) and S(1) and not(S(0));
Q(27) <= D and S(4) and S(3) and not(S(2)) and S(1) and S(0);
Q(28) <= D and S(4) and S(3) and S(2) and not(S(1)) and not(S(0));
Q(29) <= D and S(4) and S(3) and S(2) and not(S(1)) and S(0);
Q(30) <= D and S(4) and S(3) and S(2) and S(1) and not(S(0));
Q(31) <= D and S(4) and S(3) and S(2) and S(1) and S(0);
end DAC_demux_arch;
</pre>
You can see the use statements, the entity declaration, and the framework we previous discussed for the architecture. You see that there are no signals or components declared for the architecture. Then you see a whole list of combinational logic. You can see that the logical operators AND and NOT are used extensively. Also note the indexing for the STD_LOGIC_VECTORs. There is something which appears to be an assignment operator: '''<='''. This is not called an assignment; it is verbalized as "flows to" (or "flows from") to emphasize the hardware nature of VHDL. So take the last line:
<pre>
Q(31) <= D and S(4) and S(3) and S(2) and S(1) and S(0);
</pre>
The most significant bit of the ''Q'' bus flows from the logical AND of line ''D'' and all lines in bus ''S''. Pretty simple, right? There is an order of operations to VHDL (feel free to run a Google search), but you can enforce your own ordering through the use of parentheses.