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Programming the FPGA
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Revision as of 21:03, 5 July 2007
371 bytes added
,
21:03, 5 July 2007
→Controller
Line 151:
Line 151:
*** ''CE'': serial chip enable
*** ''CE'': serial chip enable
*** ''En'': internal shift enable
*** ''En'': internal shift enable
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* '''Delay'''
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** Delays input by one clock cycle.
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** inputs
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*** ''Clk'': clock
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*** ''D'': input signal
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** outputs
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*** ''Q'': output signal
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* '''Shift Reg'''
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** A 10-bit, serial-in, parallel-out shift register.
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** inputs
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*** ''Clk'': clock
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*** ''Rst'': asynchronous, active-low rest
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*** ''D'': input signal
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*** ''En'': shift enable
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** outputs
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*** ''Q'': 10-bit output bus
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