Changes

The functional block diagram for the emulator is shown to the right.  The blocks are:

The functional block diagram for the emulator is shown to the right.  The blocks are:

* 19-cycle hold

* '''19-cycle hold'''

** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data.  It ignores any additional pulses while the 19-cycle pulse is running.  It also enforces a gap of one cycle between serial words.

** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data.  It ignores any additional pulses while the 19-cycle pulse is running.  It also enforces a gap of one cycle between serial words.

** inputs

** inputs

** outputs

** outputs

*** ''Go'': 19-cycle pulse

*** ''Go'': 19-cycle pulse

* shift register

* '''shift register'''

** This is a serial-in, parallel-out, 19-bit shift register.  While the enable line is high it clocks in data.  The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.

** This is a serial-in, parallel-out, 19-bit shift register.  While the enable line is high it clocks in data.  The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.

** inputs

** inputs

*** ''Clk'': clock

*** ''Clk'': clock

** outputs: 5-bit parallel address bus; 14-bit parallel code bus

** outputs: 5-bit parallel address bus; 14-bit parallel code bus

* follow pulse

* '''follow pulse'''

** This block monitors the enable line generated by the 19-cycle hold block.  At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.

** This block monitors the enable line generated by the 19-cycle hold block.  At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.

** inputs

** inputs

** outputs

** outputs

*** ''Q'': single-cycle following pulse

*** ''Q'': single-cycle following pulse

* 5-to-32 demux

* '''5-to-32 demux'''

** This block is a 5-to-32 demultiplexer.  It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.

** This block is a 5-to-32 demultiplexer.  It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.

** inputs

** inputs

** outputs

** outputs

*** ''00:31'': 32 enable lines (on per terminal register)

*** ''00:31'': 32 enable lines (on per terminal register)

* terminal register (x32)

* '''terminal register''' (x32)

** This is a 14-bit, parallel-in, parallel-out register.  There is one terminal register for every channel.

** This is a 14-bit, parallel-in, parallel-out register.  There is one terminal register for every channel.

** inputs

** inputs

[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]

[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]

* 19-cycle hold

* '''19-cycle hold'''

** Identical to the component of the same name in the DAC emulator (see above)

** Identical to the component of the same name in the DAC emulator (see above)

* delay

* delay

** Delays all signals by one clock cycle

** Delays all signals by one clock cycle

** inputs: clock; signal in

** inputs

** outputs: signal out

*** ''Clk'': clock

* shift register

*** ''D'': signal in

** outputs

*** ''Q'': signal out

* '''shift register'''

** A 19-bit, parallel-in, serial-out shift register.  It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high.  The signal is MSB of Addr to LSB of Code.

** A 19-bit, parallel-in, serial-out shift register.  It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high.  The signal is MSB of Addr to LSB of Code.

=== Testing box ===

=== Testing box ===