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** DB = <math>2^{14}-1</math> (full scale) yields <math>V_{out} = 49.9969*V_{RefIn}</math>.
** DB = <math>2^{14}-1</math> (full scale) yields <math>V_{out} = 49.9969*V_{RefIn}</math>.
The three lines of the interface are SYNC, SCLK, and D_in. A write to the DAC begins with a falling edge of SYNC. The next 19 bits (counted off by SCLK) are saved into a shift register The next transfer begins on another falling edge of SYNC, but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. SCLK is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
The three lines of the interface are '''SYNC''', '''SCLK''', and '''D_in'''. A write to the DAC begins with a falling edge of '''SYNC'''. The next 19 bits (counted off by '''SCLK''') are saved into a shift register The next transfer begins on another falling edge of '''SYNC''', but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. '''SCLK''' is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
=== Emulator ===
=== Emulator ===
[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]
[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]
* 19-cycle hold
** Identical to the component of the same name in the DAC emulator (see above)
* delay
** Delays all signals by one clock cycle
** inputs: clock; signal in
** outputs: signal out
* shift register
** A 19-bit, parallel-in, serial-out shift register. It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high. The signal is MSB of Addr to LSB of Code.
=== Testing box ===
== The Temperature Sensor ==
== The Temperature Sensor ==
[[Image:Temp Controller Block.JPG|thumb|Temperature sensor controller functional block diagram]]
[[Image:Temp Controller Block.JPG|thumb|Temperature sensor controller functional block diagram]]
=== Testing box ===