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** outputs: 5-bit parallel address bus; 14-bit parallel code bus
** outputs: 5-bit parallel address bus; 14-bit parallel code bus
* follow pulse
* follow pulse
** This block monitors the enable line generated by the 19-cycle hold block. At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.
** inputs: asynchronous, active-low reset; clock; 19-cycle input pulse
** outputs: single-cycle following pulse
* 5-to-32 demux
** This block is a 5-to-32 demultiplexer. It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.
** inputs: 5-bit-wide select bus, data line
** outputs: 32 enable lines (on per terminal register)
* terminal register (x32)
** This is a 14-bit, parallel-in, parallel-out register. There is one terminal register for every channel.
** inputs: asynchronous, active-low reset; clock; 14-bit data bus; read-enable
** outputs: 14-bit output bus
=== Controller ===
=== Controller ===