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[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]
[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]
The functional block diagram for the emulator is shown to the right. The blocks are:
* 19-cycle hold
** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data. It ignores any additional pulses while the 19-cycle pulse is running. It also enforces a gap of one cycle between serial words.
** inputs: asynchronous, active-low reset; clock; active-low input pulse
** outputs: 19-cycle pulse
* shift register
** This is a serial-in, parallel-out, 19-bit shift register. While the enable line is high it clocks in data. The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
** inputs: asynchronous, active-low reset; data-in serial line; enable; clock
** outputs: 5-bit parallel address bus; 14-bit parallel code bus
* follow pulse
=== Controller ===
=== Controller ===