SiPM digital control board netlist

Overview
This page contains a listing of the pins of all major ICs that will be used in the SiPM digital control board, sorted by what they will be connected to. This list is mostly complete, but will be expanded and corrected as the project progresses.

Legend
The following table describes the ICs as they are referenced on this page.

FPGA Connections
This section defines some pins that must be on the FPGA, and what they must connect to. Many of these connections may also be found in the IC netlist.

User I/O pins
For these I/O pins, "Pin Name" defines the name of the pins as they will be used for our project, not the actual pin name in the FPGA schematic. The physical FPGA pins used for each of these connections will be determined later to optimize the circuitry around the FPGA.

Configuration Pins
These pins are used for the programming of the FPGA. Many of these pins revert to user I/O pins after programming is complete.

We will be using the master serial (Platform Flash) programming mode (see FPGA programming modes). Configuration pins not used in this mode are omitted from the table below. The connections that are in the table are also visually described on page 16 of the XCF01S data sheet.

Since some of the configuration pins are used for user I/O after programming, a set of logic gates might be necessary to ensure the XCF01S remains disabled following programming. By simply ORing or NORing appropriate signals with the DONE signal, integrity of user I/O signals and signals to the XCF01S can be ensured.

IC netlist
This table lists the pins on the four main ICs and shows what they should be connected to. For the FPGA pin connections, see the next section.