Programming the FPGA



The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in VHDL. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.

Open questions
Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
 * What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
 * Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component.
 * Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.

The DAC
The VHDL files can be found here.

Interface (D)
The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal. A serial communication transfers one 19-bit word:


 * A(4:0) is a 5-bit address to select the target DAC channel. A4 is the most-significant bit and transfers first.
 * DB(13:0) is a 14-bit voltage code, where $$V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}$$.
 * DB = 0 yields $$V_{out} = 0$$.
 * DB = $$2^{14}-1$$ (full scale) yields $$V_{out} = 49.9969*V_{RefIn}$$.

The three lines of the interface are SYNC, SCLK, and D_in. A write to the DAC begins with a falling edge of SYNC. The next 19 bits (counted off by SCLK) are saved into a shift register The next transfer begins on another falling edge of SYNC, but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. SCLK is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).

Emulator (D)


The functional block diagram for the emulator is shown to the right. The blocks are:
 * 19-cycle hold
 * This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data. It ignores any additional pulses while the 19-cycle pulse is running.  It also enforces a gap of one cycle between serial words.
 * inputs
 * Reset: asynchronous, active-low reset
 * CLK: clock
 * Begin: active-low input pulse
 * outputs
 * Go: 19-cycle pulse
 * shift register
 * This is a serial-in, parallel-out, 19-bit shift register. While the enable line is high it clocks in data.  The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
 * inputs
 * Reset: asynchronous, active-low reset
 * D_in: data-in serial line
 * En: enable
 * Clk: clock
 * outputs
 * Addr: 5-bit parallel address bus
 * Code: 14-bit parallel code bus
 * follow pulse
 * This block monitors the enable line generated by the 19-cycle hold block. At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.
 * inputs
 * Reset: asynchronous, active-low reset
 * Clk: clock
 * D: 19-cycle input pulse
 * outputs
 * Q: single-cycle following pulse
 * 5-to-32 demux
 * This block is a 5-to-32 demultiplexer. It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.
 * inputs
 * Select: 5-bit-wide select bus
 * Data: data line
 * outputs
 * 00:31: 32 enable lines (on per terminal register)
 * terminal register (x32)
 * This is a 14-bit, parallel-in, parallel-out register. There is one terminal register for every channel.
 * inputs
 * Reset: asynchronous, active-low reset
 * Clk: clock
 * D: 14-bit data bus
 * En: read enable
 * outputs
 * Q: 14-bit output bus

Controller (D)


The functional block diagram for the controller is shown to the right. The blocks are:
 * 19-cycle hold
 * Identical to the component of the same name in the DAC emulator (see above)
 * delay
 * Delays all signals by one clock cycle
 * inputs
 * Clk: clock
 * D: signal in
 * outputs
 * Q: signal out
 * shift register
 * A 19-bit, parallel-in, serial-out shift register. It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high.  The signal is MSB of Addr to LSB of Code.
 * inputs
 * Clk: clock
 * Reset: asynchronous, active-low reset
 * Addr: 5-bit address bus
 * Code: 14-bit code bus
 * Sh/Ld: positive-logic shift/negative-logic load
 * outputs
 * Q: serial out line

The temperature sensor
The VHDL files can be found here.

Interface (T)
The AD7314 temperature sensor uses a four-wire interface related to (and compatible with) the SPI bus protocol. The wires are: Note that the input/output notations are for slave devices (such as the temperature sensor) but are reversed for master devices (such as the FPGA). Proper SPI protocol flips the I/O polarity of CE and SCLK and crosses the SDI and SDO lines so that SDI is an input on every device and SDO is always an output. To maintain simplicity in wiring conventions we are not using proper SPI protocol, but are calling the slave input/master output line SDI and the slave output/master input line SDO so that the SDI/O notations are proper for slaves. The maximum clock rate is no higher than 10MHz. The interface, having separate input and output lines, is full-duplex; in fact the temperature sensor is unable to function in half-duplex mode. Outputs from the temperature sensor change on rising edges of SCLK, but inputs are latched on falling edges.
 * CE: Chip Enable (input), positive logic enable for SCLK
 * SCLK: Serial Clock (input), clock line supplied by external source
 * SDI: Serial Data In (input), data input line
 * SDO: Serial Data Out (output), data output line

There is only one write operation to the temperature sensor and that is used to direct the temperature sensor to enter power-down mode. We do not plan to use this mode, so the SDI input on the temperature sensor will be tied to ground.

A read operation occurs during a 16-cycle pulse of CE. The first transmitted bit will be zero, followed by ten bits of temperature data (MSB first). The remaining five bits are copies of the final data bit. After CE goes low SDO goes into a high-Z state. Temperature data is given in degrees Celsius. The format is two's-complement with two decimal places; in essence it is standard two's-complement, then the result must be divide by four after converting to decimal.

Emulator (T)


The functional block diagram for the emulator is shown to the right. The blocks are:
 * Error Flag
 * The error flag goes high if the enable line is high for 1-15 or 17+ cycles. It resets to low any time the enable line goes back to high.  It is used to notify of a "bad" transmission (not 16 cycles long).
 * inputs
 * Clk: clock
 * Rst: asynchronous, active-low reset
 * En: enable
 * outputs
 * Err: error flag
 * Shift Reg
 * An 11-bit, parallel-in, serial-out shift register that loads when not shifting.
 * inputs
 * Clk: clock
 * Rst: asynchronous, active-low reset
 * Sh/Ld: active-high shift, active-low load
 *  Par(10:0): 11-bit parallel input bus
 * outputs
 * Ser: serial output line

Controller (T)


The functional block diagram for the controller is shown to the right. The blocks are:
 * Counter
 * Counts a cycle of 17 pulses; holds En high for 11 pulses, holds CE high for 16 pulses.
 * inputs
 * Clk: clock
 * Rst: asynchronous, active-low rest
 * Go: trigger to begin cycle
 * outputs
 * CE: serial chip enable
 * En: internal shift enable
 * Delay
 * Delays input by one clock cycle.
 * inputs
 * Clk: clock
 * D: input signal
 * outputs
 * Q: output signal
 * Shift Reg
 * A 10-bit, serial-in, parallel-out shift register.
 * inputs
 * Clk: clock
 * Rst: asynchronous, active-low rest
 * D: input signal
 * En: shift enable
 * outputs
 * Q: 10-bit output bus

The ADC
The VHDL files can be found here.

Interface (A)
The AD7928 ADC has several features that we do not need: the shadow/sequencer and the multiple power modes. They could be useful for more advanced or efficient functioning of the system, but are not needed. Thus we will simplify the interface by turning these features off and running the ADC is the most basic mode.

The ADC has a four-wire interface that is compatible with the SPI bus protocol. The four lines are:
 * /CS: Active-low chip select. This line is high when the ADC is idle and goes low for 16 cycles during a conversation.  As this is active-low and the only other chip on the bus (the temperature sensor) has an active-high chip select line, it is possible to use a single chip select.  That would cause one or the other chip to always be running, which would be more information than we need or than we can send across Ethernet, but it is a possible design decision.
 * SCLK: A serial clock.
 * D_out: Serial data out line, for communications from the ADC to the FPGA. This line idles in high-Z.
 * D_in: Serial data in line, for communications from the FPGA to the ADC.

On startup the ADC requires two "dummy" conversation that write all ones to the ADC and read garbage data from the ADC.

A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC. The 12-bit control register has the following format:

The sections of the control register are:
 * Write:
 * if 0, do not update the remaining 11 bits of the control register
 * if 1, write new data to the control register
 * Seq: used for a feature we don't need: set to zero
 * DC: don't care
 * Addr(2:0): 3-bit address of channel to report on during next conversation
 * Pow(1:0): used for changing power modes: set to "11"
 * Shadow: used for a feature we don't need: set to zero
 * DC: don't care
 * Range: set to zero
 * if 0, analog input range is 0 to 2*VRef
 * if 1, analog input range is 0 to VReg
 * Coding: set to zero
 * if 0, output is twos-complement
 * if 1, output is binary-coded decimal

Thus a conversation to read the voltage only (and not update the control register would look like and a conversation to set up a read on channel A(2:0) would look like where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved.  The don't-care states in bits 9 and 2 we can set to zero.

The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation. We are going to use twos-complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.

The control interface to the FPGA core will be:
 * Clk: input: Clock line
 * Rst: input: Asynchronous, active-low reset line
 * Go: input: Pulse to begin transmission
 * Wr: input: Flag whether or not to write new data to control register
 * A(2:0): input: Address to write to control register
 * C(2:0): output: Address of data coming from ADC
 * D(11:0): output: Data from ADC
 * Done: output: Flag to tell core that new data is ready

Emulator (A)


The functional block diagram for the emulator is shown to the right. The blocks are:
 * shift in 16
 * This block is a 16-bit shift-in register with asynchronous, active-low reset and shift enable. Custom outputs select the write bit and the data bits from the input string.  This register is designed to shift all 16 cycles of a transfer, but only make use of the first 12 bits of the input.
 * inputs
 * CLK: clock
 * Rst: asynchronous, active-low reset
 * En: shift enable
 * D: data in line
 * outputs
 * Q_W: the write bit from the input string
 * Q_D: the 11 data bits from the input string
 * control reg
 * This block is an 11-bit register with asynchronous, active-low reset and a clock enable line.
 * inputs
 * CLK: clock
 * Rst: asynchronous, active-low reset
 * En: read enable
 * D: data in
 * outputs
 * Q: data out
 * 3-to-8 demux
 * This block is a 3-to-8 demultiplexer.
 * inputs
 * D: data to be demuxed
 * S: 3-bit select
 * outputs
 * Q: 8-bit output
 * error flag
 * This block generates a flag to ensure that data in the control register is in the right format (to help verify synchronization). The format is: d00ddd110000, where a "d" is a don't-care state (0 or 1).
 * inputs
 * D: data in
 * outputs
 * Err: active-high error flag
 * shift out 15
 * This block is a 15-bit shift-out register with asynchronous, active-low reset and a shift/load toggle. Custom inputs load the address (MSB first) as the first 3 bits and the data as the last 12 bits.  Idle output is a zero.
 * inputs
 * CLK: clock
 * Rst: asynchronous, active-low reset
 * Sh/Ld: shift/load toggle; active-high shift enable, active-low load enable
 * D: data in
 * A: address in
 * outputs
 * Q: data out

Controller (A)


The functional block diagram for the controller is shown to the right. The blocks are:
 * counter
 * This block is a 5-bit counter. It counts out 17 cycles: from the idle state, a pulse on the Go line begins a count of 16 cycles (during which time CS is low), then on the 17th cycle re-enters the idle state to await another pulse on Go.  The Go line is ignored during a 17-cycle run.
 * inputs
 * CLK: clock
 * Rst: asynchronous, active-low reset
 * Go: pulse to leave idle state
 * outputs
 * CS: active-low chip select
 * delayer
 * This block is a single-cycle signal delayer.
 * inputs
 * CLK: clock
 * D: signal to be delayed
 * outputs
 * Q: delayed signal
 * shift out 12
 * This block is a 12-bit shift-out register with asynchronous, active-low reset and a shift/load toggle. Custom inputs load the write bit and address bits, then fill in the remaining bits (W00AAA110000).  The register drags a trailing zero.  The output idles at zero when output is not enabled.
 * inputs
 * CLK: clock
 * Rst: asynchronous, active-low reset
 * Sh/Ld: shift/load toggle; active-high shift enable, active-low load enable
 * D_W: write bit input
 * D_A: address bits input
 * outputs
 * Q: serial output
 * shift in 15
 * This block is a 15-bit shift-in register with asynchronous, active-low reset and shift enable. Custom outputs select the address bits and data bits.
 * inputs
 * CLK: clock
 * Rst: asynchronous, active-low reset
 * Sh: shift enable
 * D: data in
 * outputs
 * A: address out
 * Q: data out