Digital control board documentation

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

Required Voltages
All components on the digital board except the DAC can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see Setting the Output Range). Digital and analog grounds must be connected as well before any testing takes place.

Power Pins
Power shall be connected to the board as follows:

Power Supply Sequencing
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:


 * 1) Ensure AGND/DGND are connected/grounded
 * 2) +5V
 * 3) -5V
 * 4) High voltage

FPGA
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

Power Details
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

Logic Standard
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a 3.3V CMOS logic standard.

EEPROM
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

Power Details
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

Flashing/Burning/Writing
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

FPGA Configuration
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

JTAG Header
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

Header Location and Size
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

Power Details
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

Pinout Table
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

The gray HALT flying lead is not connected.

JTAG Overview
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

DAC
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

Power Details
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in Power Requirements. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

Setting the Output Range
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:


 * Max output voltage = VREF*50
 * Minimum high voltage supply = VREF*50 + 10
 * Acceptable range for VREF
 * Min: 1V
 * Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

Thermal Diode
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25&deg;C. It changes at a rate of -2.20mV/&deg;C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

Pinout Table
See documentation from Analog Devices.

Channel Mapping
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

ADC
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

Power Details
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (&plusmn;1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by &plusmn;0.25V without affecting ADC precision.

Setting the Measuring Range
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

Data Interfacing
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

Channel Descriptions
This table shows what signals are monitored by the ADC.

Ethernet Controller
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

Power Details
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

Ethernet Jack
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

Ethernet Jack Pins
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).


 * Pin 1: TX+
 * Pin 2: AC coupled to DGND
 * Pin 3: TX-
 * Pin 4: RX+
 * Pin 5: AC coupled to DGND
 * Pin 6: RX-
 * Pin 7: No connection
 * Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

Crystal Oscillator
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

Bus Format and Multiplexing
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

Eurocard Connector
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in DAC Channel Mapping. Here is a table describing the purpose of pins in row A:

Row A Pinout Table
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.