FPGA Registers

State Register
A three-bit register to store the current state. inputs
 * Clk: clock
 * Rst: asynchronous, reset to zero the register (puts system into reset state)
 * En: write enable
 * D: three-bit data-in bus

outputs
 * Q: three-bit data-out bus

MAC Address Registers
A set of 12 8-bit registers to store the board's and PC's MAC addresses (in that order). Note that all bits of the register are set high upon reset as a simple way to ensure that packets sent to the PC before its address has been learned will be interpreted as a broadcast packet. inputs
 * Clk: clock
 * Rst: asynchronous reset to zero the register
 * En: write enable
 * A: 3-bit address
 * D: 12-bit data-in bus

outputs
 * Q: 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)

Temperature Register
A 10-bit register to store the most recent temperature data. A 16-bit word is actually returned for the convenience of other modules - the 10-bit value is pre-padded with zeros.

inputs
 * Clk: clock
 * Rst: asynchronous reset to zero the register
 * En: write enable
 * D: 10-bit data-in bus

outputs
 * Q: 16-bit data-out bus (data pre-padded with 6 zeros to facilitate packaging into 2-byte words)

ADC Registers
A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules. inputs
 * Clk: clock
 * Rst: asynchronous reset to zero the register
 * En: write enable
 * A: 3-bit address
 * D: 12-bit data-in bus

outputs
 * Q: 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)

DAC Registers
A set of 32 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules. inputs
 * Clk: clock
 * Rst: asynchronous reset to zero the register
 * En: write enable
 * A: 5-bit address
 * D: 14-bit data-in bus

outputs
 * Q: 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)