FPGA Idler

= (010) Idler =

The Idler Block corresponding to state 010 continuously is the default module running an "idle process". It awaits an interrupt corresponding to "Receive FIFO non-empty", unpon which it transitions to state 011 - Read.

Ports

 * Clk: [in] clock
 * ''Rst: [in] asynchronous reset


 * Eth_iINT: [in] EC interrupt pin
 * state_in: [in] 3-bit FPGA state value

Transceiver Control Lines
 * TxRx_Din: [in] EC control register return value
 * TxRx_Done: [in] "Done" signal from Transceiver.
 * TxRx_Go: [out] "Go" signal to read an EC control register byte
 * TxRX_RiW: [out] active-high read, active-low write flag
 * TxRx_Aout: [out] EC control register address (8-bit)