Synthesis ReportWed Jan 1 16:53:39 2014
Release 14.6 - xst P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Reading design: FPGA_test.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "FPGA_test.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "FPGA_test"
Output Format : NGC
Target Device : xc3s50a-4-vq100
---- Source Options
Top Module Name : FPGA_test
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Includes.vhd" in Library FPGA_BasicComp.
Package compiled.
Package compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/FileWrite.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/FileRead.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/RxReg.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/FPGA_config.vhd" in Library FPGA_BasicComp.
Package compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Receiver/ReadPpacket.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Reset/MACaddrLoad.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Transmitter/WriteDpacket.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Transmitter/WriteSpacket.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Status/GetTempVal.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Status/GetADCval.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_demux.vhd" in Library work.
Architecture behavioral of Entity dac_demux is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_follow.vhd" in Library work.
Architecture behavioral of Entity dac_follow is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_shifter.vhd" in Library work.
Architecture behavioral of Entity dac_shifter is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_register.vhd" in Library work.
Architecture behavioral of Entity dac_register is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_creg.vhd" in Library work.
Architecture behavioral of Entity adc_creg is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_demux.vhd" in Library work.
Architecture behavioral of Entity adc_demux is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_error.vhd" in Library work.
Architecture behavioral of Entity adc_error is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_shift_in16.vhd" in Library work.
Architecture behavioral of Entity adc_shift_in16 is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_shift_out16.vhd" in Library work.
Architecture behavioral of Entity adc_shift_out16 is up to date.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Temp_emulator/Temp_error.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Temp_emulator/Temp_shift.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/Regs.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Status/Querier.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/SerialOut.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Transmitter/Transmitter.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Transceiver/Transceiver.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Reset/ResetSoft.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Reset/ResetHard.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/Receiver/Receiver.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Ethernet/INTCatcher/INTCatcher.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/DAC_v2/DAC_writer.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/DAC_v2/DAC_controller.vhd" in Library FPGA_BasicComp.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/FPGA_main.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/Eth_emulator.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Temp_emulator/Temp_emulator.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_emulator.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_emulator.vhd" in Library work.
Entity compiled.
Entity (Architecture ) compiled.
Compiling vhdl file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" in Library work.
Entity compiled.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 352. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 354. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 358. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 361. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 364. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 368. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 371. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 375. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 379. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 381. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 383. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 387. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 391. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 393. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 398. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 402. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 404. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 409. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 417. Wait for statement unsupported.
ERROR:HDLParsers:1015 - "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" Line 419. Wait for statement unsupported.
-->
Total memory usage is 268460 kilobytes
Number of errors : 20 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)